Rahul M. Rao

Impacts of NBTI and PBTI on SRAM static/dynamic noise margins and cell failure probability

Negative and Positive Bias Temperature Instabilities (NBTI (in PFET) and PBTI (in NFET)) weaken MOSFETs with time. The impact of such device degradation can be severe in Static Random Access Memories (SRAMs) wherein stability is governed by relative strengths of FETs. Degradation in stability with time under ‘worst case condition’ gets more important because of reduced guard-banding due to process induced instability. In this work, circuit insights into worst-case conditions and effect of NBTI and PBTI, individually and in combination, on the stability of an SRAM cell are presented. It is shown that measurable quantities such as static noise-margin are not sufficient to completely understand the combined effect of NBTI and PBTI. Monte-Carlo simulations are performed in a 45 nm PDSOI technology to estimate the increase in cell failure probability with time. In worst case, NBTI and PBTI both degrade read stability (significantly) and writability (marginally). Further, we analyze the choice of optimal power supply considering the trade-off between short-term stability (due to process variations) and long-term stability (due to NBTI/PBTI) to achieve six-sigma confidence in SRAM cell robustness.

A Heuristic to Determine Low Leakage Sleep State Vectors for CMOS Combinational Circuits

Input vector control has been used to minimize the leakage powerconsumption of a circuit in sleep state. In this paper, we presenta novel heuristic for determining a low leakage vector to beapplied to a circuit in sleep state. The heuristic is a greedy searchbased on the controllability of nodes in the circuit and uses thefunctional dependencies among cells in the circuit to guide thesearch. Results on a set of ISCAS and MCNC benchmark circuitsshow that in all cases our heuristic returns a vector having aleakage within 5% of that of the vector obtained using an extensiverandom search, with orders of magnitude improvement incomputational speed.

SRAM Write-Ability Improvement With Transient Negative Bit-Line Voltage

Increasing variations in device parameters significantly degrades the write-ability of SRAM cells in deep sub-100 nm CMOS technology. In this paper, a transient negative bit-line voltage technique is presented to improve write-ability of SRAM cell. Capacitive coupling is used to generate a transient negative voltage at the low-going bit-line during Write operation without using any on-chip or off-chip negative voltage source. Statistical simulations in a 45-nm PD/SOI technology show a 103X reduction in the Write-failure probability with the proposed method.

Leakage and leakage sensitivity computation for combinational circuits

Leakage power is emerging as a new critical challenge in the design of high performance integrated circuits. Leakage is increasing dramatically with each technology generation and is expected to dominate system power. This paper describes a static (i.e input independent) technique for efficient and accurate leakage estimation. A probabilistic technique is presented to compute the average leakage of combinational circuits. The proposed technique gives accurate results with an average error of only 2% for the ISCAS benchmarks and accurately predict both subthreshold and gate leakage as well as the leakage sensitivities to process and environmental parameters.

Impact of NBTI and PBTI in SRAM bit-cells: Relative sensitivities and guidelines for application-specific target stability/performance

The stability and performance characteristics of Static Random Access Memories (SRAMs) are known to degrade with time due to the impact of Negative and Positive Bias Temperature Instabilities (NBTI (in PFET) and PBTI (in NFET)). In this work, we provide insights into relative sensitivities of these phenomena on speed and stability of SRAM cells. Relative impact on access time, stability, and tolerability of one phenomenon over another has been studied for different application specific (high-performance or low-power) SRAM cells. We show that high-performance SRAM cells should have lower VT drift due to PBTI compared with dense cells to contain READ stability and access time. Further, worst-case static stress poses tighter process constraints compared with alternating stress.

A Completely Digital On-Chip Circuit for Local-Random-Variability Measurement

This paper presents a completely on-chip digital circuit to measure local threshold-voltage variation using an array of identical devices under test (DUTs) stacked with a single reference device. This technique detects on-chip variation of single devices, rather than matched device pairs or SRAM cells. The variation in Vt of the DUTs is detected as variation in frequency, measured by on-chip counters, resulting in a simple digital measurement. The circuit is implemented in NMOS and PMOS versions. The standard deviation of local threshold variation measured on a chip-to-chip basis on a full wafer. The results indicate that the test-structure estimates local random mismatch in MOS current (and threshold voltage) with a small time and complexity, and thus enable technology optimization and yield improvement.

On-Chip Process Variation Detection Using Slew-Rate Monitoring Circuit

The need for efficient and accurate detection schemes to mitigate the impact of process variations on the parametric yield of integrated circuits has increased in the nm design era. In this paper, a new variation detection technique is presented that uses slew as a metric along with delay to determine the mismatch between the drive strengths of NMOS and PMOS devices. The importance of considering both of these metrics is illustrated and a new slew-rate monitoring circuit is presented for measuring slew of a signal from the critical path of a circuit. Design considerations, simulation results and characteristics of the slew-rate monitor circuitry in a 45 nm SOI technology are presented, and a sensitivity of 1 MHz/ps is achieved. This scheme can detect the threshold voltage variation in the order of mV, with a sensitivity of 0.95 MHz/mV.

Relaxing Conflict Between Read Stability and Writability in 6T SRAM Cell Using Asymmetric Transistors

We propose an asymmetric-MOSFET-based six-transistor (6 T) SRAM cell to alleviate the conflicting requirements of read and write operations. The source-to-drain and drain-to-source characteristics of access transistors are optimized to improve writability without sacrificing read stability. The proposed technique improves the writability by 9%-11%, with iso read stability being compared with a conventional 6 T SRAM cell based on symmetric-MOSFET access transistors in 45-nm technology.

Parametric yield analysis and constrained-based supply voltage optimization

Parametric yield loss has become a serious concern in leakage dominated technologies. We discuss the impact of leakage on parametric yield and show that leakage can cause yield windows to shrink by imposing a two-sided constraint on the window. We present a mathematical framework for yield estimation under device process variation for given power and frequency constraints. The model is validated against Monte Carlo simulations for an industry process and is shown to have typical error of less than 5%. We then demonstrate the importance of optimal supply voltage selection for yield maximization. We also investigate the sensitivity of parametric yield to applied frequency and power constraints. Finally, we apply the proposed framework to the problem of maximizing the shipping frequency in the presence of given yield and power constraints.

A Local Random Variability Detector With Complete Digital On-Chip Measurement Circuitry

The pronounced impact of process uncertainties on the power-performance characteristics of systems has necessitated characterization and design efforts that aim to maximize the parametric yield of the design. This paper describes a completely digital on-chip technique to measure local random variation of FET current. The measurement circuit consists of a series connection of an array of independently selectable devices and a single common load device. The voltage at the intermediate node indicates the variation from device to device, and is digitized by a voltage-controlled oscillator and on-chip frequency counters. This eliminates analog current measurements and enables very rapid, all-digital measurement of single FET variability, which can also be carried out in the field. The effectiveness of the technique is illustrated using measurements results from a test chip designed in a 45-nm SOI process.