Harri Lampinen

An optimization approach to designing OTAs for low-voltage sigma-delta modulators

High performance operational transconductance amplifier (OTA) structures for high-speed, low-voltage, switched-capacitor (SC) based sigma-delta modulator applications have been designed utilizing an efficient circuit optimization strategy presented in this paper. The main idea is to use external programs together with a circuit optimizer to construct flexible optimization algorithms. Optimization goals and constraints are derived from analytical equations and application requirements. Using a 0.35 /spl mu/m CMOS processing technology a complementary folded cascode feedforward compensated (CFCFC) OTA with 2.5 V supply obtained 470 MHz unity-gain frequency, 350 V//spl mu/s slew rate, over 74 dB gain, and over 70/spl deg/ phase margin using 10 pF load capacitances. The optimization strategy was verified by measuring fabricated CFCFC OTA and sigma-delta modulator. The measurement results demonstrate a good agreement with the simulations.

Direct conversion using lowpass sigma-delta modulation

A method for quadrature demodulation by subsampling with sigma-delta analog-to-digital converters is discussed, and a correlator receiver structure based on this method is described. The almost completely digital demodulator structure is based on second-order sampling and sigma-delta analog-to-digital converters. A theoretical performance analysis is presented, and a measurement system for the method is described. The proposed structure can be implemented on a single integrated circuit.<<ETX>>

A new dual-mode data compressing A/D converter

A new data compressing analog-to-digital converter has been designed and implemented. The converter combines a successive-approximation converter architecture with a novel control algorithm, allowing operation in both linear and data compressing modes. An experimental chip has been constructed in a 1.2 /spl mu/m double-metal double-poly CMOS process, and demonstrates over 4.5 Mhz sampling rate.

Current-sensing completion detection method for standard cell based digital system design

This paper shows how the current-sensing completion detection (CSCD) method can be applied for standard cell based digital system design. With the proposed method, conventional synchronous CMOS logic circuit blocks can easily be modified for self-timed asynchronous operation. To illustrate the usage of the method a self-timed CSCD multiplier-accumulator (MAC) was constructed. Simulation results and VHDL synthesized layouts of the CSCD MAC show that the CSCD method and the various proposed design practices can be used for the construction of self-timed asynchronous logic systems.

Circuit design for current-sensing completion detection

Circuit techniques for current-sensing completion detection (CSCD) are developed and evaluated. CSCD is a mixed analog-digital method for detecting the completion of operations in digital CMOS. The technique is therefore well suited for controlling self-timed asynchronous digital VLSI circuits. Design of an experimental CSCD chip including digital arithmetic is discussed and the performance of the chip is characterized.

Novel successive-approximation algorithms

This paper presents novel control algorithms for successive-approximation (SA) analog-to-digital (A/D) converter topologies. The developed algorithms can be used to speed up the conversion, to compress the data, to minimize the memory requirement, and to minimize the power consumption.

Dynamically biased current sensor for current-sensing completion detection

This paper presents a dynamically biased current sensor for the Current-Sensing Completion Detection (CSCD) method, which cuts off the power consumption, when the logic blocks do not operate. The proposed method is an essential improvement to all completion detection methods that use static biasing in their current sensing circuits, and where the power consumption is an important issue.

Design of a self-timed asynchronous parallel FIR filter using CSCD

This paper presents a self-timed, asynchronous, parallel finite impulse response (FIR) filter architecture capable of high-speed operation. Using self-timed, parallel structures even slow calculation blocks, such as simple multiplier-accumulators (MACs), can be used to implement high-speed filters. The building blocks are implemented using specific current-sensing completion detection (CSCD) standard cells also presented in this paper. The simulation results are very promising and especially the design of the control revealed several pitfalls and possibilities that require specific solutions when designing asynchronous circuits.

A/D converter testing with a networked prototyping board

An easily configurable, computer network connected measurement system has been constructed, which has been used to test a new kind of experimental dual-mode data compressing A/D (Analog-to-Digital) converter chip. The measurement system consists of a DSP-ASIC (Digital Signal Processor-Application Specific integrated Circuit) hardware emulator, called BOAR (Board for Object Animation and Reviewing) and several special operational modules, such as anti-alias lowpass filter, which can be connected together to construct various environments, needed for a chip under measurement.

Implementation of a self-timed asynchronous parallel FIR filter using CSCD

This work presents various implementation issues of the self-timed asynchronous parallel finite impulse response (F1R) filter. The main objective was to design all the necessary operational blocks using VHDL and commercial electronic design automation (EDA) tools in order to prove that asynchronous current-sensing completion detection (CSCD) circuits can be designed with traditional EDA tools targeted originally for synchronous designs. In order to make the design steps more effective, some improvements for the EDA software have also been proposed including the graphical control block design in a single design window and the design space exploration method for logic synthesis.