Harry Li

Body-driving as a low-voltage analog design technique for CMOS technology

This paper presents an overview of circuit topologies for achieving low-voltage analog designs using body-driving techniques. A new and novel low-voltage Class AB output stage is presented along with topologies for amplifiers and a four quadrant multiplier. A discussion of the application of body-driving in a silicon-on-insulator (SOI) technology is also included.

A radiation-hard phase-locked loop

Phase-locked loops (PLLs) are often used as frequency multiplier for generating high frequency clock signals. In space application, however, performance of the normal PLL is degraded due to the radiation effects. In this paper, several aspects of a rad-hard PLL are investigated, including radiation effects, radiation hardening techniques, PLL building blocks and the overall performance. This circuit is developed using the Peregrine 0.50 /spl mu/m SOS/SOI process. The post-layout simulation result indicates that the circuit can be used to generate 100 M - I80 MHz programmable clock signal under radiation conditions with process, temperature and voltage variations. The maximum peak to peak jitter is less than 100 ps while the maximum lock-in time is less than 20 us under typical conditions.

Power Management and Distribution for System on a Chip for Space Applications

In this paper a method for achieving integrated power electronics is discussed. Future spacecraft are projected to feature high levels of integration at the system level (i.e., a “systems on a chip” approach) particularly in areas not typically associated with an integrated approach (such as inertial reference systems, RF communications, imaging, sensors, etc.). Taking full advantage of the miniaturization occurring in these other systems will require commensurate reductions in the size of the power electronics. Power electronics are traditionally larger due to the need for high value passive components requiring significant power handling capabilities. Our approach takes advantage of lower projected power requirements and utilizes integrated, on-chip passives and novel high voltage transistors to achieve adaptive distributed on-chip power management and distribution (PMAD). Operating from a single supply, this on-chip PMAD will operate at power levels of up to 1 W, at frequencies of 110 MHz. INTRODUCTION Integrated systems on future nanosatellites will get their supply voltage from a common power bus. These systems will rely on efficient adaptive on-chip power management circuits for generating the internal voltage levels necessary for operation of the sensors, actuators and other subsystems. For space applications, there are several challenges in building an efficient completely integrated power management system, including a) the development of a new generation of miniaturized large value passive components (inductors and capacitors) for DC-DC converter circuits that can be integrated on-chip, b) the development of on-chip power interrupt protection (such as microbatteries), c) the development of high voltage transistors that can coexist with traditional low voltage transistors in the same radiation hardened silicon substrate, and d) the development of a library of mixed-signal/mixedvoltage CMOS cells suitable for the construction of a completely integrated on-chip power management system. This paper summarizes JPL’s effort in overcoming the challenges of building a completely integrated power management system for future avionics microsystems for deep space applications for NASA. PMAD REQUIREMENTS FOR AVIONICS SYSTEM ON A CHIP Figure 1 shows the block diagram of a proposed on-chip adaptive power management system for the next generation of highly miniaturized satellites. Principle components in this on-chip power management system are switching DC-DC converters with large value onchip inductors and capacitors, micro batteries, battery charge/discharge circuits and digital 110 circuits for interface and control. Digital Interface Bus 12C Main Satellite Power Bus

Temperature-independent high voltage reference design in silicon-on-insulator CMOS technology

Temperature independence for voltage reference circuits designed in silicon-on-insulator CMOS technology. This design takes advantage of high-voltage devices recently developed for a 0.35 um process. This paper focuses on unique aspects of design in this process, using a voltage reference as a vehicle. The underlying circuit is a high voltage reference, designed in a diode configuration and in a MOSFET configuration. Layout considerations common to both of the circuits are outlined. Design equations are developed. Performance is characterized through SPICE simulations.

MOSFET charger controller circuit for on chip power cells in aeronautical applications

Integrated microbatteries are being currently developed to act as a “micropower” source in microsatellites. They help provide localized current capacities or embedded power supplies at the chip level, for space exploration. These power cells are designed to be rechargeable. This research paper aims at presenting charging these power cells using pulsing algorithms developed at MRCI with an on chip pulse charger controller.

Essentials of SOI technology for small power supply applications

The relationship between that of silicon-on-insulator (SOI) technology and ordinary CMOS is presented followed with an examination of the basic features of MOSFETs fabricated under the SOI process. Such features include the intrinsic junction diodes, diffusion capacitance, floating-body effect, internal parasitic bipolar effects, the insulation layer and its consequences, and the self-heating effect. In addition to the fact that many of these features provide improvements in transistor design and performance over standard CMOS, SOI technology is poised to become competitive for small power supply applications.