Hasan Baig

D-VASim: an interactive virtual laboratory environment for the simulation and analysis of genetic circuits

Simulation and behavioral analysis of genetic circuits is a standard approach of functional verification prior to their physical implementation. Many software tools have been developed to perform in silico analysis for this purpose, but none of them allow users to interact with the model during runtime. The runtime interaction gives the user a feeling of being in the lab performing a real world experiment. In this work, we present a user-friendly software tool named D-VASim (Dynamic Virtual Analyzer and Simulator), which provides a virtual laboratory environment to simulate and analyze the behavior of genetic logic circuit models represented in an SBML (Systems Biology Markup Language). Hence, SBML models developed in other software environments can be analyzed and simulated in D-VASim. D-VASim offers deterministic as well as stochastic simulation; and differs from other software tools by being able to extract and validate the Boolean logic from the SBML model. D-VASim is also capable of analyzing the threshold value and propagation delay of a genetic circuit model. AVAILABILITY AND IMPLEMENTATION D-VASim is available for Windows and Mac OS and can be downloaded from bda.compute.dtu.dk/downloads/. CONTACT haba@dtu.dk, jama@dtu.dk.

A Low-Overhead Multiple-SEU Mitigation Approach for SRAM-based FPGAs with Increased Reliability

The mitigation of single-event upsets (SEUs) through modular or functional redundancy is a traditional approach for designing fault-tolerant systems; however, even in multiple redundant systems, SEUs can lead to a system failure if they occur simultaneously. Previous fault-tolerant approaches have proposed run-time reconfiguration to regain the lost functionality. We worked with a similar strategy to overcome failures caused by unidirectional SEUs occurring simultaneously in both frontline and redundant modules, but the approach we propose in this paper not only improves reliability but also requires low-overhead as compared to previous methodologies. The proposed architecture is an array of computation tiles containing computation cells and corresponding hot-spares. Each computation tile has a separate region for spare cells. The simultaneous faults are handled by an on-chip fault-tolerant core and external host software that partially reconfigure the spare-cells region of a computation tile. The proposed architecture is implemented on a Xilinx Virtex-5 FPGA device and verified with the aid of simple digital application. Compared to previous schemes, our approach requires up to 9.6x less area overhead while providing 57.6% more reliability to mask multiple unidirectional SEUs.

An island-style-routing compatible fault-tolerant FPGA architecture with self-repairing capabilities

In this work, we have developed a fault-tolerant architecture which is compatible with existing island-style routing network. Due to this compatibility, the proposed architecture can not only be implemented easily in the existing FPGA devices but a new fault-tolerant FPGA device can also be fabricated without refining the existing routing architecture. A generic fault-tolerant Computation Cell is developed which along with its self-checking circuitry also consists of an internal router to route un-faulty function out of the cell. The proposed fault-tolerant FPGA architecture is comprised of Computation Tiles each of which consists of computation cells which are able to heal themselves from transient errors. Computation Tile also contains stem cells which help computation cells to recover from permanent errors all at once. This architecture is centrally controlled by an on-chip fault-tolerant core whose main responsibility is to define the healing priority when an error occurs in more than one of the computation tile at the same time. It also communicates with the external PC software which identifies the faulty tile and reconfigures it through dynamic partial reconfiguration. The robust operation of a proposed architecture is implemented and verified on XILINX Virtex-5 FPGA device. From our proposed fault-tolerant scheme of utilizing the existing routing strategies together with partial reconfiguration of stem cells we achieved a number of benefits, including a fast fault recovery and avoidance of using complicated routing strategies, as compared to recently developed fault-tolerant FPGA architectures.

Implementation of SCADA system for unsought tablets detection through morphological image processing

Pharmaceutical industries which are intended for the packaging of different tablets in a strip of blister need to make sure that the tablets are free from defects before letting them go into the packing box. The purpose of this paper is to introduce an efficient, reliable and cost effective supervisory control and data acquisition (SCADA) system for detection and removing of unwanted tablet(s) strips. The system detects defective tablets by capturing image of a batch of tablets and performs morphological analysis over it. If a defective tablet is found, the system is smart enough to trace in which strip the defective tablet would be present after cutting of batch and hence instructing the remote terminal unit (RTU) to remove that strip. The status of the whole process at the completion of every order is sent to master terminal unit (MTU) which generates and saves the log file on MS-EXCEL, and is also able to send the log file to main server via electronic mail.

Simulation Approach for Timing Analysis of Genetic Logic Circuits

Constructing genetic logic circuits is an application of synthetic biology in which parts of the DNA of a living cell are engineered to perform a dedicated Boolean function triggered by an appropriate concentration of certain proteins or by different genetic components. These logic circuits work in a manner similar to electronic logic circuits, but they are much more stochastic and hence much harder to characterize. In this article, we introduce an approach to analyze the threshold value and timing of genetic logic circuits. We show how this approach can be used to analyze the timing behavior of single and cascaded genetic logic circuits. We further analyze the timing sensitivity of circuits by varying the degradation rates and concentrations. Our approach can be used not only to characterize the timing behavior but also to analyze the timing constraints of cascaded genetic logic circuits, a capability that we believe will be important for design automation in synthetic biology.

Logic analysis and verification of n-input genetic logic circuits

Nature is using genetic logic circuits to regulate the fundamental processes of life. These genetic logic circuits are triggered by a combination of external signals, such as chemicals, proteins, light and temperature, to emit signals to control other gene expressions or metabolic pathways accordingly. As compared to electronic circuits, genetic circuits exhibit stochastic behavior and do not always behave as intended. Therefore, there is a growing interest in being able to analyze and verify the logical behavior of a genetic circuit model, prior to its physical implementation in a laboratory. In this paper, we present an approach to analyze and verify the Boolean logic of a genetic circuit from the data obtained through stochastic analog circuit simulations. The usefulness of this analysis is demonstrated through different case studies illustrating how our approach can be used to verify the expected behavior of an n-input genetic logic circuit.

Taming Living Logic Using Formal Methods

One of the goals of synthetic biology is to build genetic circuits to control the behavior of a cell for different application domains, such as medical, environmental, and biotech. During the design process of genetic circuits, biologists are often interested in the probability of a system to work under different conditions. Since genetic circuits are noisy and stochastic in nature, the verification process becomes very complicated. The state space of stochastic genetic circuit models is usually too large to be handled by classical model checking techniques. Therefore, the verification of genetic circuit models is usually performed by the statistical approach of model checking. In this work, we present a workflow for checking genetic circuit models using a stochastic model checker (Uppaal) and a stochastic simulator (D-VASim). We demonstrate with experimentations that the proposed workflow is not only sufficient for the model checking of genetic circuits, but can also be used to design the genetic circuits with desired timings.

A novel run-time auto-reconfigurable FPGA architecture for fast fault recovery with backward compatibility (abstract only)

A self-repairing fault-tolerant FPGA architecture is developed which is also compatible with existing island-style routing network. Due to this backward compatibility, the proposed architecture can not only be implemented easily in the existing FPGA devices but a new fault-tolerant FPGA device can also be fabricated utilizing the existing island-style routing architecture. A generic fault-tolerant Computation Cell is developed which can be incorporated in existing FPGA CLB (Configurable Logic Block) having 8 LUTs at least. The proposed fault-tolerant FPGA architecture is comprised of Computation Tiles each of which consists of computation cells which are able to heal themselves from transient errors. Computation Tile also contains stem cells which help computation cells to recover from permanent errors all at once. This architecture is centrally controlled by an on-chip fault-tolerant core whose main responsibility is to define the healing priority when an error occurs in more than one of the computation tile at the same time. It also communicates with the external PC software which identifies the faulty tile and reconfigures it through dynamic partial reconfiguration. The robust operation of a proposed architecture is implemented and verified on XILINX Virtex-5 FPGA device. From our proposed fault-tolerant scheme of utilizing the existing routing strategies together with partial reconfiguration of stem cells we achieved a number of benefits, including a fast fault recovery and avoidance of using complicated routing strategies, as compared to recently developed fault-tolerant FPGA architectures.

A Novel Automated Experimental Approach for the Measurement of On-Chip Speed Variations through Dynamic Partial Reconfiguration

In this research we have developed a complete automated experimental setup for the measurement of on-chip delay variations through dynamic partial reconfiguration. The experiment is performed on two different Virtex-5 devices on the basis of which intra-die and inter-die speed comparisons have been made. We developed an on-chip sensor map consisting of 60 sensors out of which only alternating sensors remains active at a time. This is done to avoid affects of inter-sensor heat dissipation. Once finished collecting the data, on-chip processor communicates with the sensor hardware to extract and encode the data, and send it to the online Graphical User Interface implemented on the LabVIEW platform. Afterwards, the processor dynamically loads another bitstream from the Compact Flash Memory Card to activate another alternate group of sensors to perform remaining analysis. While using the same sensor topology we found the intra-die speed variations of up to 6-10%. However, inter-die speed comparison result depicts that one chip is 2-10% faster than another one.