Hassan El-Ghitani

Accelerating Matrix Multiplication on FPGAs

In this paper we present a new architecture for fixed-point matrix multiplication using Xilinx Virtex4 device. The architecture effectively utilizes the hardware resources on the entire FPGA and makes use of DSP blocks inside the FPGA devices. The architecture also reduces the routing complexity. Our architecture can be implemented for non-square matrix multiplication. The proposed implementation shows improvement in area and latency compared to recent published work. An improvement by over 50% in FMAX and 20% in area using new FPGAs has been achieved.

A 0.4V 90nm CMOS subthreshold current conveyor

This paper presents a new low power Current Conveyor II (CCII). The proposed circuit uses a 0.4 V single-ended supply. The advantages of the proposed current mode readout circuit are threefold. Firstly, the proposed circuit provides extremely low power consumption while operating all MOSFETs in the subthreshold region providing the highest energy efficiency. Secondly, Self cascode technique is used to increase the gain of the differential amplifier to 65 dB. Finally, it is based on standard CMOS technology which can be easily used in VLSI circuits. Near perfect voltage/current tracking up to 1.25 / 0.8 MHz was achieved while consuming 1.7 μW.

Analysis and design of analog-based voltage controlled oscillator linearization technique

This paper analyzes an analog technique for VCO linearization based on a switched-capacitor feedback loop. The analysis covers both inversely and directly proportional VCOs. Based on this analysis, design criteria for determining the best loop parameters are presented using a look-up table. In addition, the tradeoffs between the linearized VCO tuning range, dynamic range, and loop settling speed are marked out. Simulation results show that the above analysis allowed the design of a linearization loop which improved the non-linearity of a 2 GHz tuning range VCO from 8% to 0.4%.

Design of low power CMOS subthreshold current mode instrumentation amplifier based on CCII

This paper describes the design of a low power current mode instrumentation amplifier dedicated to biomedical applications based on current conveyor. All MOSFETs operate in the subthreshold region yielding high energy efficiency using a single ended 0.4V supply. Its designed using standard CMOS technology which can be easily integrated into VLSI circuits. The design procedure is explained and verified by post layout results presented using TSMC 90 nm technology. Chopping technique is applied to reduce flicker noise to 3.59 μVrms for bandwidth 0.2–150 Hz. A high common mode rejection ratio of 107 dB is achieved while consuming 5.5 μW with maximum gain 41 dB. The chip area is 0.023 mm2. The obtained results demonstrate that well designed current mode circuits in subthreshold are an attractive solution for portable biomedical applications.

A balanced signal generator for lab on chip dielectrophoresis (DEP) levitation techniques

Dielectrophoresis (DEP) is the phenomenon where a force is exerted on a particle when a non-uniform electric field is applied. Its commonly used in separating cancer cells from healthy cells or separating different strains of bacteria. DEP requires 2 perfectly out of phase signals with matched amplitude for controlling the electrical field. This paper presents a low power balanced signal generator based on the operational floating current conveyor (OFCC) for the use in lab-on-chips that use DEP levitation. The OFCC is a versatile analog current mode building block. The circuit is designed using standard TSMC 90 nm CMOS technology. The circuit consumes 11 μW from a 0.4 V single supply. The total chip area is 0.053 mm2. The generator outputs 2 signals with 0.03 dB difference in amplitude and 5 degrees in phase at 1 MHz. Post layout simulation show that the circuit provides a promising solution for Lab-on-Chip using DEP levitation techniques.

A Case-Based Reasoning Approach for the Automatic Generation of VHDL-AMS Models

Automatic generation of analog and mixed-signal (AMS) behavioral models from specifications is an important component of top-down design methodologies. In this paper, we present an expert system solution to this challenge. Based on a representation of the model functionality, our expert system manipulates a library of previously developed models to synthesize a new model. Automatically generated VHDL-AMS behavioral models are shown to be of expert quality.

Behavioral modeling of a charge pump voltage converter for SoC functional verification purposes

To enable full chip functional verification, critical system building blocks need to be abstracted and simplified using behavioral models. Charge pump voltage converters are highly active circuits and act as bottle necks when integrated in SoC verification simulations. In this paper, a charge pump circuit designed by STMicroelectronics will be modeled using VHDL-AMS. Using this model, the whole SoC can be simulated by ADVance MStrade.

A programmable 8-bit, 10MHz BW, 6.8mW, 200MSample/sec, 70dB SNDR VCO-based ADC using SC feedback for VCO linearization

A low power linearized 8-bit VCO-based ADC is presented. The proposed ADC employs a differential VCO coupling technique to enhance the VCO time resolution and a linearization switched capacitor feedback loop for improving the SNDR and VCO linearity. The loop added the programmability property to the ADC performance. The 200MSample/sec ADC was implemented in 130nm CMOS process showing an SNR/SNDR ranging from 91.4/88.3dB to 54.3/41.2dB for an input bandwidth of 500kHz-100MHz while consuming a total of 6.78mW from a 1.2V supply. The process insensitive linearization loop improves the VCO linearity from 2% to 0.17%.

A programmable 8.3mW, 0.5–100MHz BW, 88.3–48.1dB SNDR VCO-based ADC with switched capacitor linearization

A low power linearized 9-bit VCO-based ADC is presented. The proposed ADC employs a differential VCO coupling technique to enhance the VCO time resolution and a linearization switched capacitor feedback loop for improving the SNDR of the ADC. The proposed 200MHz ADC implemented in 130nm CMOS process showed an SNR/SNDR ranging from 91.4/88.3dB to 54.3/41.2dB for an input bandwidth of 500kHz - 100MHz while consuming a total of 8.3mW from a 1.2V supply.