Hazem Said

Chameleon ART: a non-optimization based analog design migration framework

Presented in this paper is a tool that automatically migrates analog designs from one process to another while keeping circuit and layout topologies. A netlist migration engine recalculates the new device dimensions in the target technology followed by a layout migration engine that compacts the design according to the new process design rules. The overall framework preserves design intelligence embedded in the original IP such as symmetry, hierarchy, placement and routing. The circuit migration engine, being very fast, can retarget large analog blocks in only a few minutes while giving same or better performance of the original design. The migration of 3 different circuits is presented to validate the overall methodology. These circuits have been fabricated and measured

Analog Layout Retargeting

This chapter focuses on analog layout process retargeting. Unlike automatic placement and routing tools, retargeting starts with an input layout in 6 a given process. The main target is to conserve most of the layout physical intelli- gence while migrating it to another given technology. This is usually achieved by adapting existing layout compaction techniques borrowed from the digital world. Historically, layout compaction used to rely on fast constraint-graph operations. More recently, linear programming has been introduced to support hierarchy in ad- dition to complex analog constraints. This chapter introduces a novel graph-based simplex algorithm that combines the efficiency of graph-based methods together with the generality of linear programming ones. It also allows symmetry, hierar-chy, and cell replacement support to be integrated seamlessly without any artificial modification of the algorithm. For simple layout constraints, the algorithm com- plexity tends to be as linear as graph-based techniques, while for the most complex constraints and objective function it tends to that of the simplex method.

A Novel General Graph-Based Simplex Algorithm Applied to IC Layout Compaction and Migration

In this paper, a novel method for solving the IC layout compaction problem is introduced. The solution supports all kinds of linear constraints and linear optimization functions. Graph-based techniques are employed so that all matrix operations in linear programming are replaced by much faster graph operations. The proposed algorithm outperforms all studied compaction methods by combining the generality of linear programming and the efficiency of graph-based methods. Correct and optimal migrated layouts were produced with significant improvement in performance.

Complete Properties Extraction from Simulation Traces for Assertions Auto-generation

Machine learning techniques based on Data Miningare employed for automatic assertion generation in hardwaredigital design verification. This paper presents a new miningtechnique to extract all design properties from simulation traces.The extracted properties cover all possible design assertionseither at system level or Register Transfer Logic (RTL)verification depending on the simulated design level. It canafterwards be tuned or filtered to match a certain desiredabstraction level. The new technique is based on a Breadth-FirstDecision Tree (BF-DT) search algorithm. The innovatedalgorithm maps the input simulation traces to a search tree thatcovers all possible input combinations, and prunes the redundantpaths. The proposed technique is tested against recentlyinnovated mining techniques for some basic digital designfunctions as a proof of concept for the gained efficiency. Themain advantage of the new technique is the possibility to extractall the design properties from the simulation traces achievinghundred-percent coverage in a reasonably efficient time formillions of simulation traces.

New Methodology for Complete Properties Extraction from Simulation Traces Guided with Static Analysis

This paper introduces a new methodology for digital design properties extraction from simulation traces. A new Breadth-First Decision Tree (BF-DT) mining algorithm is proposed for complete properties extraction from simulation traces. The new mining engine supports both bit-level and word-level values of different design variables. Static analysis technique is implemented to extract all data dependencies between the digital design variables. New traces regeneration algorithm is proposed to obtain reduced traces for more efficient and easier mining. The mining engine is guided with these data dependencies to extract complete design properties relating target variables desired to extract properties for and their cone of interest feature variables. The contributed mining technique has been tested for different designs with different sizes. The design properties generated from the mining engine completely match with all design properties covered in the input simulation traces. Moreover, the generated properties are at the highest possible level of abstraction leading to the best coverage for the input data space. The simulation results show that the proposed methodology has superior efficiency in extracting both bit-level and word-level complete assertions of digital design in both superior quality and feasible time.

HMM based automatic Arabic sign language translator using Kinect

In this paper, a new Arabic sign language automatic translator is presented. The translator is based on Hidden Markov Models (HMMs). The features used in recognition are 3D information detected using Microsoft Kinect Sensor depth camera. The system was trained to recognize 40 signs from standard Arabic sign language. A go-stop scheme is presented to handle sequences of signs which construct sentences in real-time. The recognition success rate based on the new methodology is above 90 percent with real time performance on a PC.

Optimally matched current mirror layout pattern generation using genetic optimization

This paper introduces an automatic current mirror layout generation tool for any number of transistors and for arbitrary integer current ratios. The paper uses an adapted form of genetic optimization to minimize the overall systematic mismatch due to oxide gradients. Results show that very low mismatches are obtained in a few seconds for moderate sized arrays.

A generalized Grover's algorithm with access control to quantum databases

Quantum databases are considered the next generation for databases. They are suspected to be very fast and secure using the quantum features and quantum security algorithm. Through this paper, a system for a quantum database and an algorithm that selects from it are going to be suggested based on generalized Grovers algorithm.

Quantum databases: Trends and challenges

Quantum computing field is evolving rapidly these days. The difference between this new field and the classical field is the extension of the main domain from just using two bits (0, 1) to a complete space which is the result of the superposition of the same mentioned bits. By applying the superposition property in the quantum algorithms, this ensures that the system is more secured than the classical one and gives the quantum algorithms the advantage of breaking the classical ones. Databases, like any other system, require security due to the fact that it contains massive amounts of information that needs to be accessed only by the right user. The following survey will take a more in depth look into quantum databases.

New methodology for digital design properties extraction from simulation traces

This paper introduces a new methodology for digital design properties extraction from simulation traces. The innovated methodology is based on a new data mining technique guided with static analysis of the intended design. The mining engine of the proposed methodology is based on innovated Breadth-First Decision Tree (BF-DT) search algorithm. The data structure of each node in the decision tree is handled to well present sub-space of the input simulation traces data space. Besides, new features are added to BF-DT to enhance its performance in both output sequential assertions and time of search. A new static analysis technique is innovated to extract all the combinational and sequential data dependencies between the digital design signals. The mining engine is guided with these data dependencies to extract complete combinational and sequential design properties relating signals desired to extract properties for and their cone of interest signals. The contributed mining technique has been tested for bit-level designs with different sizes. The design properties generated from the mining engine completely match with all design properties covered in the input simulation traces. Plus, the generated properties are at the highest possible level of abstraction leading to the best coverage for the input data space. The simulation results show that the proposed methodology has proven superior efficiency in extracting bit-level assertions of digital design in a feasible time. The next challenge is to include word-level assertions as well.