Ayman M. Wahba

Design error diagnosis in sequential circuits

We present a new diagnostic algorithm for localising design errors in sequential circuits. The specification and the implementation may have different number of state variables, and different state encoding. The algorithm is based on the new concept of possible next states describing the possible states of the circuit due to the existence of the error. Results obtained on benchmark circuits show that the error is always found, with an execution time proportional to the product of the circuit size, and the length of the test sequences used.

A method for automatic design error location and correction in combinational logic circuits

We present a new diagnostic algorithm, based on backward-propagation, for localising design errors in combinational logic circuits. Three hypotheses are considered, that cover all single gate replacement and insertion errors. Diagnosis-oriented test patterns are generated in order to rapidly reduce the suspected area where the error lies. The originality of our method is the use of patterns which do not detect the error, in addition to detecting patterns. A theorem shows that, in favourable cases, only two patterns suffice to get a correction. We have implemented the test generation and diagnosis algorithms. Results obtained on benchmarks show that the error is always found, after the application of a small number of test patterns, with an execution time proportional to the circuit size.

Connection Errors Location and Correction in Combinational Circuits

We present new diagnostic algorithms for localizing connection errors in combinational circuits. Three types of errors are considered: extra, missing, and bad connection errors. Special test patterns are generated to rapidly locate the error. The algorithms are integrated within the Prevail/sup TM/ system. Results on benchmarks show that the error is always located within a time proportional to the product of the circuit size, and the number of used patterns.

HDL-Based Integration of Formal Methods and CAD Tools in the PREVAIL Environment

We present an open environment for the integration of formal methods applied to HDL descriptions of circuits. The system currently accepts SMAX[4] and VHDL, and provides equivalence checking, model checking, theorem proving, and automatic diagnosis of simple design errors. After an overview of the system, we discuss the salient features of the common intermediate format, of the diagnosis tools, and of the automatic generation of NQTHM[11] models from VHDL functional descriptions.

Verification and Diagnosis of Digital Systems by Termary Reasoning

Ternary vectors {0,1,X} may be used to simulate binary systems more efficiently than binary vectors. It has recently been shown by R.E. Bryant that formal verification by ternary simulation is feasible. In this paper, we demonstrate that complete verification of Finite State Machines is possible by ternary simulation. The verification vectors are derived from AND/OR trees. We also show how design error diagnosis can be performed by utilizing the difference vector set. Algorithms for the diagnosis of single inverter errors, and wrong gate type, are presented, together with illustrative examples.

Automatic diagnosis may replace simulation for correcting simple design errors

An automated tool for diagnosing simple design errors in VHDL description is presented. The tool is tested on benchmark circuits, and the results show that the error is localized precisely, after the application of a small number of specially generated test patterns. This tool is now integrated within the PREVAIL/sup TM/ system, and is being tested on industrial circuits.

HYBRID-BASED MAINTAINABILITY IMPACT ANALYSIS FOR EVOLVING SYSTEMS

Software maintenance becomes an integral part of software life cycle and constitutes the most important fraction of the total cost of the software lifecycle. Around 50–80 percent of the total lifec...