Min-Kyu Song

A full accuracy MPEG1 audio layer 3 (MP3) decoder with internal data converters

A full accuracy MPEG1 audio layer 3 (MP3) decoder with internal A/D converter and D/A converter is proposed. The chip is composed of a digital block to implement MP3 decoding and voice compression/decompression algorithm, a 12-bit recycling type A/D converter, and an oversampling /spl Delta//spl Sigma/ 1-bit D/A converter. In order to satisfy the full accuracy specification of MP3 decoder, a novel 32-bit floating DSP core is proposed. Further, an efficient power management technique is implemented to reduce power consumption for portable applications. The proposed decoder has been fabricated with a 4 metal 0.35 um CMOS technology and the chip area is about 6.4x6.7 mm/sup 2/ with 165 mW power dissipation at 2.7 V power supply.

An 8-b 1GS/s Fractional Folding CMOS Analog-to- Digital Converter with an Arithmetic Digital Encoding Technique

A fractional folding analog-to-digital converter (ADC) with a novel arithmetic digital encoding technique is discussed. In order to reduce the asymmetry errors of the boundary conditions for the conventional folding ADC, a structure using an odd number of folding blocks and fractional folding rate is proposed. To implement the fractional technique, a new arithmetic digital encoding technique composed of a memory and an adder is described. Further, the coding errors generated by device mismatching and other external factors are minimized, since an iterating offset self-calibration technique is adopted with a digital error correction logic. A prototype 8-bit 1GS/s ADC has been fabricated using an 1.2V 0.13 um 1-poly 6-metal CMOS process. The effective chip area is 2.1 mm 2 (ADC core : 1.4 mm 2 , calibration engine : 0.7

A low power full accuracy MPEG1 audio layer III (MP3) decoder with on-chip data converters

A low power full accuracy MPEG1 audio layer 3 (MP3) decoder with on-chip data converters is proposed. The chip is composed of a digital block to implement MP3 decoding and voice compression/decompression algorithm, 12-bit recycling type A/D converter, and an oversampling /spl Delta//spl Sigma/ 1-bit D/A converter. An efficient power management technique is implemented to reduce power consumption for portable applications. The proposed decoder has been fabricated with a 4 metal 0.35 /spl mu/m CMOS technology and the chip area is about 6.4/spl times/6.7 mm/sup 2/ with 165 mW power dissipation at 2.7 V power supply.

A Low Power Dual CDS for a Column-Parallel CMOS Image Sensor

In this paper, a 320 × 240 pixel, 80 frame/s CMOS image sensor with a low power dual correlated double sampling (CDS) scheme is presented. A novel 8-bit hold-and-go counter in each column is proposed to obtain 10-bit resolution. Furthermore, dual CDS and a configurable counter scheme are also discussed to realize efficient power reduction. With these techniques, the digital counter consumes at least 43% and at most 61% less power compared with the column-counters type, and the frame rate is approximately 40% faster than the double memory type due to a partial pipeline structure without additional memories. The prototype sensor was fabricated in a Samsung 0.13 ㎛ 1P4M CMOS process and used a 4T APS with a pixel pitch of 2.25 ㎛. The measured column fixed pattern noise (FPN) is 0.10 LSB.

A 10 bit 30 MSPS CMOS A/D converter for a high performance video application system

In a video application system, an A/D converter which converts the analog signal into digital codes plays an important role in determining the system performance. In this paper, a high performance A/D converter which has 10-bit resolution and 30 MSPS conversion speed is proposed. It has an architecture of pipeline style. With 0.5 /spl mu/m double poly and double metal fully CMOS technology, the experimental prototype of the proposed A/D converter has /spl plusmn/0.7 LSB INL, and /spl plusmn/0.5 LSB DNL.

Design methodology for low power data compressors based on a window detector in a 54/spl times/54 bit multiplier

Currently, a typical 54/spl times/54 bit multiplier is composed of a parallel structured architecture with the encoder block to implement the Modified Booths algorithm, a block to implement the data compression, and a 108-bit Carry Look-Ahead (CLA) adder. The key idea is a design methodology for the low power data compressors based on an intelligent window detector. The role of the window detector is detecting the input data, choosing the optimized output data, and driving the next stage. Furthermore, it can reduce the power consumption drastically because only one optimized operation unit (a window) is activated. Therefore, it can be called an intelligent window detector. Using it, the average power consumption of the proposed data compressors is reduced by about 35%, compared with that of the conventional multiplier; while the propagation delay is nearly same as that of the conventional one.

A 10-b 500 MS/s CMOS Folding A/D Converter with a Hybrid Calibration and a Novel Digital Error Correction Logic

A 10-b 500 MS/s A/D converter (ADC) with a hybrid calibration and error correction logic is described. The ADC employs a single-channel cascaded folding-interpolating architecture whose folding rate (FR) is 25 and interpolation rate (IR) is 8. To overcome the disadvantage of an offset error, we propose a hybrid self-calibration circuit at the open-loop amplifier. Further, a novel prevision digital error correction logic (DCL) for the folding ADC is also proposed. The ADC prototype using a 130 ㎚ 1P6M CMOS has a DNL of ±0.8 LSB and an INL of ±1.0 LSB. The measured SNDR is 52.34-㏈ and SFDR is 62.04-㏈c when the input frequency is 78.15 ㎒ at 500 MS/s conversion rate. The SNDR of the ADC is 7-㏈ higher than the same circuit without the proposed calibration. The effective chip area is 1.55 ㎟, and the power dissipates 300 ㎽ including peripheral circuits, at a 1.2/1.5 V power supply.

A 45 nm 9-bit 1 GS/s High Precision CMOS Folding A/D Converter with an Odd Number of Folding Blocks

In this paper, a 9-bit 1GS/s high precision folding A/D converter with a 45 nm CMOS technology is proposed. In order to improve the asymmetrical boundary condition error of a conventional folding ADC, a novel scheme with an odd number of folding blocks is proposed. Further, a new digital encoding technique is described to implement the odd number of folding technique. The proposed ADC employs a digital error correction circuit to minimize device mismatch and external noise. The chip has been fabricated with 1.1V 45nm Samsung CMOS technology. The effective chip area is 2.99 mm 2 and the power dissipation is about 120 mW. The measured result of SNDR is 45.35 dB, when the input frequency is 150 MHz at the sampling frequency of 1 GHz. The measured INL is within +7 LSB/-3 LSB and DNL is within +1.5 LSB/-1 LSB.

Design of a low power 54/spl times/54 bit multiplier based on an intelligent window detector

In this paper, a design methodology of a low power 54/spl times/54 bit multiplier based on a Window Detector is proposed. This multiplier is composed of a parallel structured architecture with the encoder block to implement the Modified Booths algorithm, a block to implement the data compression, and a 108-bit Carry Look-Ahead (CLA) adder. The key idea is the design of a Window Detector which implements the block of data compression. The role of the Window Detector is detecting the input data, choosing the optimized output data, and driving the next stage. Furthermore, it can reduce the power consumption drastically because only one optimized operation unit (a Window) is activated. Therefore, it can be called an intelligent Window Detector. Using it, the power consumption of the proposed multiplier is reduced by about 50%, compared with that of the conventional multiplier, while the propagation delay is not much more than that of the conventional one.

Iron Corrosion Protection by Ultra-thin Conductive Films Based on Polypyrrole/Poly(methyl methacrylate) Composite

ABSTRACT The metallic surfaces can be protected from the corrosive media by conducting polymer coating which provides passivation mechanism by redox chemistry. Their poor solubility and processibility were improved by the use of soluble polypyrrole (PPy) and composite with poly(methyl methacrylate) (PMMA). Soluble PPy was synthesized by controlling the monomer-to-oxidant ratio in the presence of dodecylbenzenesulfonic acid (DBSA) as a dopant. And then MMA was mixed with PPy/m-cresol solution to spin-coat onto iron. The 4-probe method was used to measure electrical conductivity and FTIR spectra were used to study the conjugation length of PPy. Scanning electron microscopic (SEM) images were obtained to observe the surface morphology. Tafel plots showed that the PMMA/PPy composite film caused a positive shift of around 200 mV in the corrosion potential and the anodic current decreased by two orders of magnitude compared with bare iron.