Heiko Hinkelmann

Towards a unique FPGA-based identification circuit using process variations

A compact chip identification (ID) circuit with improved reliability is presented. Ring oscillators are used to measure the spatial process variation and the ID is based on their relative speeds. A novel averaging and postprocessing scheme is employed to accurately determine the faster of two similar-frequency ring oscillators in the presence of noise. Using this scheme, the average number of unstable bits i.e. bits which can change in value between readings, measured on an FPGA is shown to be reduced from 5.3% to 0.9% at 20°C. Within the range 20 – 60°C, the percentage of unstable bits is within 2.8%. An analysis of the effectiveness of the scheme and the distribution of the errors is given over different temperature ranges and FPGA chips.

Design Concepts for a Dynamically ReconfigurableWireless Sensor Node

Wireless sensor networks require the design of highly energy-efficient and yet flexible sensor nodes, which is very difficult to realize with classical architectures. In this paper we propose a new approach based on the tight coupling of a small processor with a dynamically reconfigurable function unit that is optimized for wireless sensor network applications. Dynamic reconfiguration is part of the regular operation mode and the key concept to achieve a small design that provides sufficient performance, high adaptivity and good energy-efficiency

A Domain-Specific Dynamically Reconfigurable Hardware Platform for Wireless Sensor Networks

In this paper, a new generic sensor node platform for wireless sensor networks (WSN) is presented, demonstrating that high energy efficiency, flexibility and performance can be achieved by the use of dynamically reconfigurable hardware in the WSN domain. The core of the presented platform is formed by the combination of a RISC processor and a dynamically reconfigurable function unit optimized for efficient data processing in WSN applications. A novel reconfiguration mechanism is applied enabling rapid dynamic reconfiguration with very short latencies. Thereby, we can show that the overhead on performance and energy consumption caused by dynamic reconfiguration can be reduced to a moderate, non-critical value and is clearly outweighed by the significantly improved performance and energy consumption for data processing on the reconfigurable function unit. The evaluation of the platform and its comparison to a standard processor-based platform finally demonstrate high gains in energy-efficiency of one to two orders of magnitude.

On the design of reconfigurable multipliers for integer and Galois field multiplication

Multiplication is a vital function for practically any DSP system. Some common DSP algorithms require different multiplication types, specifically integer or Galois Field (GF) multiplication. Since both functions share similarities in their structures, the potential is given for efficiently combining them in a single reconfigurable VLSI circuit, leading to competitive designs in terms of area, performance, and power consumption. This will be analysed and discussed in detail for 10 reconfigurable multiplier alternatives that are based on different strategies for the combination of integer and GF multiplication. Each result is compared to a reference architecture, showing area savings of up to 20% at a marginal increase in delay, and an increase in power consumption of 25% and above. This gives evidence that function-specific reconfigurable circuits can achieve considerable improvements in at least one design objective with only a moderate degradation in others. From this perspective, function-specific reconfigurable circuits can be considered feasible alternatives to standard ASIC solutions.

A Reconfigurable Prototyping Platform for Smart Sensor Networks

In this paper, a new concept for a very flexible and modular prototype platform for rapid prototyping of wireless sensor networks is presented. We propose to use a FPGA with high gate count as core of the platform. The FPGA is utilized to attain 3 major goals for the prototype platform: to emulate arbitrary mote architectures even including smart motes with high system complexity, to realize flexible interfaces to sensors and radio transceivers, and to embed versatile debugging and system monitoring functionality in the mote prototypes. The presented prototype platform is suitable to realize complete sensor networks based on different mote architectures, different wireless communication schemes, and arbitrary application domains. The design concepts and implementation aspects of the platform are presented and discussed in detail.

Design and evaluation of an energy-efficient dynamically reconfigurable architecture for wireless sensor nodes

We explore the design of a coarse-grained reconfigurable architecture for wireless sensor network nodes, which combines high energy efficiency with programmability and hence meets the requirements of small energy-constraint embedded systems. Its energy consumption, area, and performance are evaluated and compared to processor and ASIC architectures. Our case study particularly focuses on the question if the architecture concept of frequent dynamic reconfiguration of a small heterogeneous data path can lead to suitable system solutions for the target domain. To answer this, the effect of the reconfiguration overhead on total system efficiency is examined closely. As important result, our experiments show the low energy consumption achieved, the low reconfiguration overhead, and the specific region of the architecture in the design space between processors and ASICs. In particular, large energy-savings of factor 2 to 6 and speed-ups of factor 6 to 14 compared to processors are obtained on average. Our work shows the high suitability of frequent runtime reconfiguration of small coarse-grain data paths for the design of very efficient but yet programmable embedded systems platforms.

A Power Estimation Model for an FPGA-Based Softcore Processor

We describe the application of a hybrid functional level power analysis (FLPA) and instruction level power analysis (ILPA) approach to a processor model implemented on an FPGA. This technique enables the estimation of the task specific power consumption of the modeled processor, in our case a LEON2, very early during a system design flow, based on the software which will run on it. The FLPA/ILPA model used during our work as well as the test scenarios and the measured results are described. Later, the function block separation and the power consumption modeling are discussed. Finally, the model is validated by benchmarking. The obtained model is promising in the sense that a) its estimations are close (4 % on average) to the measured data, and b) the model structure is similar to that of hardcore processors which is not a trivial result.

A Methodology for Wireless Sensor Network Prototyping with Sophisticated Debugging Support

In this paper, we present a methodology for rapid prototyping of wireless sensor networks that allows to embed sophisticated debugging functionality in a mote prototype and thereby monitor entire networks. We achieve this goal by combining two fundamental concepts: the use of a re-configurable sensor node prototype platform, and an auxiliary network structure for granting a reliable communication channel for runtime debugging without interfering with the primary radio link. For the prototype platform, we propose a modular design which incorporates a single FPGA with high gate count as core of the platform. The FPGA is utilized to emulate arbitrary mote architectures and realize flexible interfaces to sensors and radio transceivers. As a major benefit, versatile debugging interfaces can additionally be implemented in the same FPGA, seamlessly integrating into the emulated mote architecture, with direct access to internal information. This easily allows to realize passive system monitors as well as active debugging control. By using a deployment support network to exchange relevant information, all motes can be monitored and controlled simultaneously by a user. The paper presents the proposed methodology, its implementation, and a practical application example in detail.

A switch architecture and signal synchronization for GALS system-on-chips

Increasing power consumption and growing design effort are considered limiting factors in the design of chip-wide synchronous system-on-chip designs. The attempt to get over these problems lead to an intensified look at asynchronous communication solutions, sometimes based on network-on-chips. Despite this basically asynchronous approach, most of the actual research work is not supporting a globally genuinely-asynchronous solution. We present a modular switch for a true globally asynchronous interconnect network. Independent clock generators in each switch maintain a local clock thus avoiding a global clock at the level of the interconnect network. The general switch architecture is described and the integration of the synchronization technique used to resolve metastability is discussed in detail. First synthesis results of a prototypical VLSI implementation are presented.

An integrated tool flow to realize runtime-reconfigurable applications on a new class of partial multi-context FPGAs

Efficient cycle-based reconfiguration of datapaths can be realized on current FPGAs by designing merged datapaths, which can execute different tasks depending on the datapath control. In our previous work, we provided a synthesis tool for the automated generation of such datapaths. The objective in this paper is a reduction of the resource requirements for implementing the reconfiguration control on the FPGA. First, we extend our existing tool flow with a novel mechanism for efficient partial multi-context reconfiguration and provide tool support to generate according circuitry, control, and configuration data. Second, we propose an extension of current FPGA architectures to efficiently support cycle-based runtime control. We employ a special contentaddressable multi-context memory resource for controlling the datapath functionality, which on average requires only 15% memory for storing the control data compared to a BlockRAM based approach, and only 53% compared to regular multi-context switching.