Tudor Murgan

The XPP Architecture and Its Co-simulation Within the Simulink Environment

This paper offers an overview of the XPP, a coarse-grained reconfigurable architecture, and presents a solution for its integration into a Simulink design flow for rapid prototyping. This includes a system-level co-simulation followed by the automated code generation for an embedded target platform. In order to realize this functionality, a custom Simulink module has been developed. During the co-simulation phase, it acts as a wrapper for an external simulator, whereas when code is generated, it is responsible for generating the appropriate function calls for communicating with the XPP device. Of these two aspects, only the co-simulation is considered here.

Low-Power Coding for Networks-on-Chip with Virtual Channels

Power consumption represents a major concern for Networks-on-Chip (NoC). In order to provide quality-of-service to such NoCs, Virtual Channels are normally used. A drawback of the approach is the increased power consumption because of the suppression of correlation between consecutive flits. This work proposes a low-power coding approach to overcome the aforementioned problem. The technique requires a minimum overhead, while obtaining a significant power reduction. Exhaustive experimental simulations are provided to demonstrate the advantages of the proposed architecture.

Reconfigurable platforms for ubiquitous computing

Ubiquitous computing requires flexibilty. Melting distributed electronic devices into everydays life implies the need to adapt to evolving standards and dynamic environments. Furthermore, to gain user acceptance, such devices should be able to adapt to different usage patterns and user profiles. Scalability is also an important issue, allowing functional enhancements to already deployed systems. In this work we address these issues applying the concept of reconfigurability on different abstraction layers. Concerning the physical layer we discuss multistandard and standard update capabilities, dynamic power management and functional optimisation. Within this context we consider important design issues related to on-chip communication networks. Furthermore, dynamic reconfigurable processor architectures are analyzed with respect to applications in communications. Finally, in the service layer, we address device location, interconnection and clustering.

Power estimation based on transition activity analysis with an architecture precise rapid prototyping system

In this paper a technique is proposed to gather statistical data concerning transition activity of the interface signals in a complex application. By using an architecture precise rapid prototyping system, the signals can be analyzed over a long period of time and therefore a realistic estimation of the signal activity characteristics can be obtained. This information can be used for estimating the power consumption in the final system as well as for a later refinement of the communication structures and single processing blocks. Because of the huge amount of data that would be generated by a real time monitoring, a statistical compression module was implemented. This module allows the trade off between hardware efficiency and accuracy in order to offer a flexible use in prototyping systems. The proposed approach has been validated in a baseband implementation of a simplified OFDM transmitter.

Moment-Based Power Estimation in Very Deep Submicron Technologies

The significant power optimization possibilities in the early stagesof the design flow advice the use of energy evaluation techniquesat high levels of abstraction. With this aim, the present work addressesthe estimation of the energy consumption in very deep submicrontechnologies. Using the characterization of the probabilitydensity function with a projection in an orthogonal polynomialbase, and a symbolic propagation mechanism, a technique is presentedto estimate the dynamic and static power consumption indigital systems. The proposed approach has been validated withcircuits and excitations from realistic applications. Comparisonswith reference transistor and bit level simulations are reported inorder to asses the the accuracy of the technique.

Partial bus-invert bus encoding schemes for low-power DSP systems considering inter-wire capacitance

In this work, we develop simple yet very effective bus encoding schemes that dramatically reduce both self and coupling transition activity in common DSP signals. We show that, efficient low-power codes must cope with the different statistical characteristics of the most and least significant bits. On one hand, the high correlation in the most significant bits can be exploited by employing a simple non-redundant code. On the other hand, Bus Invert based codes are very efficient when applied only on the poorly correlated uniformly distributed least significant bits. The latter should not be employed on the most significant bits in order to preserve their high correlation. Additionally, we show that low-power codes can be easily compared by means of a simple graphical method.

Power consumption in point-to-point interconnect architectures

As technology shrinks, the importance of the communication architecture in the overall system performance and power consumption increases dramatically. In this work, a framework is developed to estimate the consumption in point-to-point interconnect structures under different anti-crosstalk techniques and bus encoding schemes. To model the effect of cross coupled capacitances, the spatial correlation between adjacent bus lines is considered. Assuming that the data has a Gaussian distribution, both temporal and spatial transition activities are estimated from the signal world level statistics using a polynomial function of the activity in the most significant bit. Analog simulations have been carried out to show the accuracy of the proposed model.

On the necessity of combining coding with spacing and shielding for improving performance and power in very deep sub-micron interconnects

In this work, the necessity of combining signal encoding schemes with low-level anti-crosstalk techniques like spacing and shielding is analyzed. It is shown that in order to increase the throughput improvement and/or reduce the power consumption, coding schemes should be integrated with layout techniques since methods like spacing and shielding can be regarded as very simple encoding schemes. On this basis, a theoretical framework for assessing the improvement in throughput and/or power consumption is constructed. Furthermore, several possibilities to integrate coding with classical anti-crosstalk techniques are discussed.

Functional modeling techniques for a wireless LAN OFDM transceiver

This paper presents a systematic approach to modeling and simulating an OFDM transceiver for wireless LAN using SystemC. On the one hand, it shows the problems associated with using pure untimed dataflow models, suggesting different solutions for circumventing them and adds run-time control features to modules. On the other hand, it proposes a method for modeling latency (adds timing information) with minimal overhead on the model complexity. For both the timed and the untimed dataflow models, two approaches to transferring data between modules are presented: sample-based and symbol-based, which results in four possible modeling scenarios.

On timing and power consumption in inductively coupled on-chip interconnects

This work analyses the effects on timing and power consumption of the inductive coupling in long high-frequency on-chip interconnects. By means of extensive simulations it is shown that the common assumptions used until now when considering only line inductance effects do not hold. In fact, signal integrity, voltage glitches and cross-talk, signal delay, rise and fall times, as well as power dissipation strongly depend on the mutual inductances and the input data toggling pattern.