Heiko Weichert

Effect and procedures of post exposure bake temperature optimization on the CD uniformity in a mass production environment

Controlling a very tight CD budget in Photolithography is one of the challenges of the next technology nodes. The Post Exposure Bake (PEB) process is known as one of the main Litho contributors to CD non-uniformity for processes using resists with moderate or high PEB sensitivity. However, to achieve a good CD uniformity plate to plate (PtP) and within plate (WiP) - the current temperature calibration procedures of PEB plates will not be sufficient enough to fulfil the requirements of future technology nodes. TELs CD Optimizer - which is a software integrated to the Coater / Developer using a mathematical model based on scatterometry CD data and the PEB sensitivity of the resist - allows an accurate PtP and WiP CD uniformity adjustment. Compared to the conventional time consuming temperature calibration procedures the CD Optimizer can improve the CD uniformity significantly - and it saves lots of productive time. This method already has been confirmed by using bare Si wafers [1]. We will show for the first time the effect of the CD optimization on the CD uniformity of production wafer in a high-volume 300mm DRAM FAB. We did analyse CD mass production data obtained from Integrated Metrology (IM) scatterometry measurements before and after optimization of the PEB plates. We can also show that it is possible to use IM mass production data for the PEB temperature optimization directly.

CDU improvement with wafer warpage control oven for high-volume manufacturing

Immersion lithography has been developed for 45nm technology node generation during the last several years. Currently, IC manufacturers are moving to high volume production using immersion lithography. Due to the demand of IC manufactures, as the critical dimension (CD) target size is shrinking, there are more stringent requirements for CD control. Post Exposure Bake (PEB) process, which is the polymer de-protection process after exposure, is one of the important processes to control the CD in the 193nm immersion lithography cluster. Because of the importance of the PEB process for CD uniformity, accurate temperature control is a high priority. Tokyo Electron LTD (TEL) has been studying the temperature control of PEB plates. From our investigation, total thermal history during the PEB process is a key point for controlling intra wafer and inter wafer CD [1]. Further, production wafers are usually warped, which leads to a nonuniform thermal energy distribution during the PEB process. So, it is necessary to correct wafer warpage during the baking process in order to achieve accurate CD control on production wafers. TEL has developed a new PEB plate for 45nm technology node mass production, which is able to correct wafer warpage. The new PEB plate succeeded in controlling the wafer temperature on production wafers using its warpage control function. In this work, we evaluated CD process capability using the wafer warpage control PEB plate, which is mounted on a CLEAN TRACKTM LITHIUS ProTM-i (TEL) linked with the latest immersion exposure tool. The evaluation was performed together with an IC manufacturer on their 45nm production substrates in order to determine the true performance in production.

Integrated ODP Metrology Matching To Reference Metrology For Lithography Process Control

Advanced DRAM manufacturing demands rigorous and tight process control using high measurement precision, accurate, traceable and high throughput metrology solutions. Scatterometry is one of the advanced metrology techniques which satisfies all of these requirements. Scatterometry has been implemented in semiconductor manufacturing for monitoring and controlling critical dimensions and other important structural parameters. One of the major contributing factors to the acceptance and implementation of scatterometry systems is the ability to match to reference metrology. Failure to understand the optimum matching conditions, can lead to wrong conclusions with respect to hardware stability and/or incorrect analysis of production data. This paper shows the use of the integrated scatterometry system to control the lithography processes in a real production environment. In the control system, the scatterometry Optical Digital Profilometry (ODP™) data is referenced to sampled CD‐SEM data. A significant improvemen...

Initial process evaluation for next generation immersion technology node

In order to prepare for the next generation technology manufacturing, ASML and TEL are working together to investigate the process performance of the LITHIUSi+/ TWINSCAN XT:1700i lithocluster through decreasing critical dimension patterning. In this evaluation, process performance with regards to critical dimension uniformity and defectivity are compared at different critical dimensions in order to determine areas of concentration for equipment and process development. Specifically, design of experiments were run using immersion rinse processing at 60nm hp and 45nm hp. Defects were classified to generate a pareto for each technology node to see if there is any change in the defect types as critical dimensions are shrinking. Similarly, critical dimension uniformity was compared through technology nodes to see if any budget contributions have increased sensitivities to the smaller patterning features. Preliminary gauge studies were performed for the 45nm hp evaluation, as metrology at this design rule is not yet fully proven. More work is necessary to obtain complete understanding of metrology capabilities as this is crucial to discern precise knowledge of processing results. While preliminary results show no adverse impact moving forward, this work is a first screening of 45nm immersion processing and more work is needed to fully characterize and optimize the process to enable robust manufacturing at 45nm hp.

Application of integrated scatterometry measurements for a wafer-level litho feedback loop in a high-volume 300 mm DRAM production environment

With critical dimensions in microelectronics devices shrinking to 70nm and below, CD metrology is becoming more and more critical, and additional measurement information will be needed, especially for sidewall profiles and profile height. Integrated scatterometry is, on the one hand, giving the needed measurement precision, and on the other hand, it enables more measurements than stand-alone metrology. Both high precision and large sampling are needed for future technology nodes. This paper shows results from several full volume DRAM applications of state-of-the-art technology nodes on 300 mm wafers. These applications include critical line/space (L/S) layers as 2D applications and contact-hole (CH) layers consisting of elliptical CH-like structures as critical 3D applications. The selected applications are significantly more challenging with respect to scatterometry model generation than the applications presented in previous papers [1, 2]. Simultaneously, they belong to the most critical lithography steps in DRAM manufacturing. In the experiments, the influences of both pre-processes and the litho cluster on Critical Dimension Uniformity (CDU) have been investigated. Possible impacts on Run-to-Run systems like Feed-back and Feed-forward loops will also be discussed. We show that using integrated scatterometry can significantly increase the productivity of lithography clusters.