Heinrich Theodor Vierhaus

CMOS bridges and resistive transistor faults: IDDQ versus delay effects

Beyond the static stuck-at fault model, delay fault testing and static overcurrent testing have been suggested as approaches yielding reasonable fault coverage in CMOS circuits. Based on detailed simulations of resistive stuck-on-, stuck-open-, and bridging faults for typical CMOS circuits, this paper presents an analysis of their detectability and requirements for current and timing resolutions in overcurrent and delay fault testing.<<ETX>>

Mixed Level Hierarchical Test Generation for Transition Faults and Overcurrent Related Defects

Automatic test pattern generation yielding high fault coverage also for non-trivial faults in CMOS circuits has found a wide attention in industry and research for a long time. Test generation from gate level netlists is quite efficient, but has shortcomings with respect to fault coverage in complex CMOS gates, while an approach relying on the transistor structure only is inefficient and virtually impossible for larger circuits. This paper describes mechanisms for coupling switch level and gate level test generation towards an efficient mixed level test generator that combines acceptable performance for large networks and high fault coverage also for non-trivial transistor networks. Patterns generated this way are inherently capable to detect interrupt-types of faults and transition faults. In combination with local overcurrent detectors, also stuck-on- and bridging faults can be identified.

Improving topological ATPG with symbolic techniques

This paper presents a new approach to Automatic Test Pattern Generation for sequential circuits. Traditional topological algorithms nowadays are able to deal with very large circuits, but often fail when highly sequential subnetworks are found. On the other hand, symbolic techniques based on Binary Decision Diagrams proved themselves very efficient on small or medium circuits, no matter their sequential complexity. A state-of-the-art structural ATPG is extended by identifying some critical areas in the circuit and resorting to symbolic techniques when such areas need to be considered. Experimental results prove that the combined approach considerably enhances fault coverage while reducing CPU time when compared to a purely topological approach.

MILEF: an efficient approach to mixed level automatic test pattern generation

Automatic test pattern generation in CMOS circuits from gate-level net lists is efficient, but has shortcomings with respect to fault coverage in complex and irregular CMOS gates and networks. An approach relying on the transistor structure only is inefficient and virtually impossible for larger circuits. The authors describe the gate level part of a tool for dynamically coupled gate-level and switch-level test generation. Acceptable performance and high fault coverage for non-trivial transistor networks are combined. Patterns generated in this way are inherently capable of detecting interrupt types of faults and transition faults. In combination with local overcurrent detectors, stuck-on and bridging faults can be identified.<<ETX>>

Efficient partitioning and analysis of digital CMOS-circuits

A library independent method for the partitioning and analysis of switch-level CMOS circuits is presented. This method is superior to the existing methods for extraction, because it is able to recognize CMOS tristate drivers connected to a bus individually. Moreover, it can improve the state-of-the-art algorithms for the determination of unidirectional signal flow, because its functional analysis is able to recognize groups of transistors which always constitute signal sources. The local functional analysis of the partitions is improved by the exclusion of impossible paths. Additionally, the recognition of fully complementary gates allows the improvement of existing algorithms for signal flow analysis.<<ETX>>

SymFony: a hybrid topological-symbolic ATPG exploiting RT-level information

Combining different techniques for sequential automated test pattern generation (ATPG) can help overcome their respective limits and exploit their advantages. In this paper, a hybrid technique resulting from mixing topologic and symbolic approaches to the sequential ATPG problem is presented. Macros are first identified within the circuit (possibly resorting to RT-level knowledge of circuit architecture). Information about macro behavior is then computed and efficiently stored resorting to symbolic techniques. A topological tool exploits this information during the ATPG process to speed-up the propagation task and to identify early unsuccessful choices. Experimental results are reported, demonstrating that the method is able to improve the efficiency of a topological ATPG in terms of required CPU time and attained fault coverage, especially on medium-sized control-dominated circuits.

Local Microcode Generation in System Design

Codesign is a promising methodology for reducing the time to market of embedded systems. Retargetable code generation is one of the critical problems that must be solved efficiently for this methodology to succeed. This chapter shows that optimizing the critical basic blocks of the code has a considerable impact on the performance of the designed systems. We introduce an automata-theoretic model of (local) microcode generation for basic blocks, and propose a practical solution to this optimization problem. Our method can be integrated into various design flows that use retargetable code generation.

Automatic test pattern generation with optimal load balancing

Test patterns are used to prove the correct functionality and absence of manufacturing faults after producing a chip. The automatic generation of those test patterns for sequential circuits is harder than NP-complete problems and therefore an interesting algorithm to parallelize.

Fault behavior and testability of asynchronous CMOS circuits

Abstract Asynchronous circuits have not yet found a widespread application in VLSI chips despite their inherent advantages over synchronous circuits, notably a higher speed potential. This may partly be attributed to testing problems. This paper describes the fault behavior of typical basic asynchronous CMOS circuits under realistic fault conditions and suggests some basic approaches towards testable design.

CMOS transistor faults and bridging faults: Testability by delay effects and overcurrents

Abstract Testing CMOS circuits for faults which cannot safely be detected by static test patterns has been a matter of intense research for years. Recently methods based on delay fault models have been developed for a safe detection of dynamic faults. At the same time, test methods based on overcurrent effects have found new interest due to the application of built-in current monitoring elements. This paper analyses some typical types of defects in CMOS circuits for their detectability either by delay effects or overcurrents. Advances and limitations of both basic approaches are discussed.