B. Wunderle

Through silicon via technology — processes and reliability for wafer-level 3D system integration

3D integration is a rapidly growing topic in the semiconductor industry that encompasses different types of technologies. The paper addresses one of the most promising technologies which uses through silicon vias (TSV) for interconnecting stacked devices on wafer-level to perform high density interconnects with a good electrical performance at the smallest form factor for 3D architectures. Fraunhofer IZM developed a post frontend 3D integration process, the so- called ICV-SLID technology based on metal bonding using solid-liquid-interdiffusion (SLID) soldering. The SLID metal system provides the mechanical and the electrical connection, both in one single step. The ICV-SLID fabrication process is well suited for the cost-effective production of both, high- performance applications (e.g. 3D microprocessor) and highly miniaturized multi-functional systems. The latter preferably in combination with wafer-level die stacking, as e.g. Thin Chip Integration (TCI) or SnAg-microbump technologies. The fabrication of distributed wireless sensor systems (e. g. e-CUBESreg) is a typical example for the need of such mixed approaches.

Forced convective interlayer cooling in vertically integrated packages

The heat removal capability of area-interconnect-compatible interlayer cooling in vertically integrated, high-performance chip stacks was characterized with de-ionized water as coolant. Correlation-based predictions and computational fluid dynamic modeling of cross-flow heat-removal structures show that the coolant temperature increase due to sensible heat absorption limits the cooling performance at hydraulic diameters les 200 mum. An experimental investigation with uniform and double-side heat flux at Reynolds numbers les 1000 and heat transfer areas of 1 cm2 was carried out to identify the most efficient interlayer heat-removal structure. Parallel plate, microchannel, pin fin, and their combinations with pins using in-line and staggered configurations with round and drop-like shapes at pitches ranging from 50 to 200 mum and fluid structure heights of 100 to 200 mum were tested. A hydrodynamic flow regime transition responsible for a local junction temperature minimum was observed for pin fin inline structures. The experimental data was extrapolated to predict maximal heat flux in chip stacks with a 4-cm2 heat transfer area. The performance of interlayer cooling strongly depends on this parameter, and drops from >200 W/cm2 at 1 cm2 and >50 mum interconnect pitch to <100 W/cm2 at 4 cm2.

High aspect ratio TSV copper filling with different seed layers

The paper addresses the through silicon via (TSV) filling using electrochemical deposition (ECD) of copper. The impact of seed layer nature on filling ratio and void formation will be discussed with respect to via diameter and via depth. Based on the spherolyte Cu200 the electrolyte for the copper electrochemical deposition was modified for good filling behavior. Thermomechanical modeling and simulation was performed for reliability assessment.

Heat-removal performance scaling of interlayer cooled chip stacks

Interlayer cooling is the only heat removal concept which scales with the number of active tiers in a vertically integrated chip stack. In this work, we numerically and experimentally characterize the performance of a three tier chip stack with a footprint of 1cm2. The implementation of 100µm pitch area array interconnect compatible heat transfer structures results in a maximal junction temperature increase of 54.7K at 1bar pressure drop with water as coolant for 250W/cm2 hot-spot and 50W/cm2 background heat flux. The total power removed was 390W which corresponds to a 3.9kW/cm3 volumetric heat flow.

Progress in reliability research in the micro and nano region

Abstract Due to the rapid development of IC technology the traditional packaging concepts are making a transition into more complex system integration techniques in order to enable the constantly increasing demand for more functionality, performance and miniaturisation. These new concepts will have to combine smaller structures and layers made of new materials with even higher reliability. As these structures will more and more display nano-features, a coupled experimental and simulative approach has to account for this development to assure design for reliability in the future. A necessary “nano-reliability” approach as a scientific discipline has to encompass research on the properties and failure behaviour of materials and material interfaces under explicit consideration of their nano-structure and the effects hereby induced. It uses nano-analytical methods in simulation and experiment to consistently describe failure mechanisms on that length scale for more accurate and physically motivated lifetime prediction models for use on a larger (i.e. then the micro) scale. This paper deals with the thermo-mechanical reliability of microelectronic components and systems and methods to analyse and predict it. Various methods are presented to enable lifetime prediction on system, component and material level, the latter introducing the field of nano-reliability for nano-packaging in advanced electronics system integration.

Molecular dynamics approach to structure–property correlation in epoxy resins for thermo-mechanical lifetime modeling

This paper addresses the potential of molecular dynamics simulation for structure-property correlations in epoxy-resins. This is an important topic within a multi-scale framework to lifetime prediction in electronic packaging. For that purpose, epoxy-resins with small systematic variations in chemical structure have been synthesised and then characterised by various thermo-mechanical testing methods. It was found that moisture diffusion showed the greatest response with respect to material and loading parameters such as polarity, free volume, moisture concentration and temperature. Based on a parametric study, modeling approaches of various complexity have been able to show f rst qualitative but then also quantitative agreement. The paper comments further on the accuracy and limits of the method and correlates the calculations with experimental structural analysis results.

Structure property correlation of epoxy resins under the influence of moisture; and comparison of diffusion coefficient with MD-simulations

The properties of epoxy based materials alter, when exposed to humid environment and temperature. To better understand the failure mechanisms on microelectronic packaging we examine these epoxies (aromatic epoxy: l,3-Bis-(2,3-epoxypropyl)-benzene and amine hardener: 1,2-Diaminoethan ) under different initial conditions of temperature (300-400 K) & humidity (85,100 RH) and change systematically the structure (stoichiometry & molecular weight). By applying the previous conditions we perform mechanical characterization (glass transition temperature-Tg & coefficient of thermal expansion - CTE), make diffusion experiments to obtain the diffusion coefficient D , the water uptake-wt%, the hygroscopic strain epsiv and do molecular dynamics-(MD) simulations to calculate the D and compare them with experiment. Diffusion coefficients are calculated under NVT - thermodynamic boundary conditions by using a classical force-field MD. It was found that changing the free-volume and/or polarity of the structure does influence the properties and molecular dynamics predicted qualitatively the influence of structure on D.

Delamination and combined compound cracking of EMC-copper interfaces

The present study deals with experimental investigation of the delamination toughness of EMC (epoxy molding compound) and Copper-leadframe interfaces. Test samples were directly obtained from the production line. EMC is attached on copper substrates with various surface treatments. Mixed mode bending experiments were performed under various temperature and moisture environments. The test procedure and some results were reported previously in ECTC08 and ECTC09 [1–2]. Recently, we studied the effect of delaminated surfaces in order to get better understanding of the established fracture toughness. Therefore, after the delamination experiments, some of the delaminated samples were subjected to various surface analyses (SEM, FIB, EDX). Two types of failure patterns are found depending on the loading mode mixture, and the environmental conditions. Firstly, depending on the type of copper surface treatment, pure interface delamination is observed for some of the interfaces. Here, we observed clean delaminated copper surfaces. The second type of failure is a combination of interface delamination and compound cracking. Here, it is found that after the separation of interfaces, some EMC remains on the copper surface. In this case the experiment results showed that the interface delamination and molding compound cracking combined failure occurs at relatively high force values.

Parametric FE-approach to flip-chip reliability under various loading conditions

In this paper we focus on the thermo-mechanical reliability of flip-chip assemblies which are, in addition to periodic thermal loads, constrained by mechanical boundary conditions caused by the attachment of a heat-spreader. Whereas mechanically unconstrained flip-chip assemblies have been in the focus of reliability studies for a long time, the loading induced by additional mechanical constraints and hence the impact on solder bump reliability is still largely unknown. So a comprehensive study was carried out comprising FE-simulations for lifetime prediction and thermal cycling tests for experimental verification. For this purpose a tool for modular parametric FE-model generation was developed. The experiments do coincide with the simulative prediction with good accuracy, allowing for the first time a distinct statement about the reliability of flip-chip packages with attached heat-spreaders. As a result we have found that in general all additional constraints on the chip do reduce its lifetime. A distinct ranking has be obtained as a function of the specified variables. Eventually design guidelines are given.

Interfacial fracture parameters of silicon-to-molding compound

The rapid diversification in microelectronics forebodes more complex system integration, be it for denser function integration or a span of dimensions between various technologies. Products may include more features, perform faster and be cheaper. With these trends the amount of material layers is increasing. This challenges development to a faster rating of material pairings. Delamination is a major issue among the related reliability aspects. When the design or testing steps are accompanied by simulation, fracture mechanical descriptions are increasingly proving helpful. The parameters needed for simulation have to be measured and should be available for different fracture mode mix angles. We investigated the interfacial fracture toughness of the Epoxy Molding Compound (EMC) to Silicon interface. Although difficult to delaminate we could carry out measurements using the Mixed Mode Chisel setup (MMC) that allowed us to induce different stress states at the crack tip at various external load angles. The samples we derived from the molding process of embedded wafer level ball grid arrays. Therefore we were able to use samples made with the same process as in real packaging. The crack tip position was determined by analysis of displacement results by digital image correlation. In order to interpret the sample reaction for extracting fracture mechanical parameters, adequate numerical modeling and simulation was required. The experiments provided the parameters for the models. Establishing the residual stress state in the materials preceded the interface delamination simulation: a two step interpretation. Residual stresses cannot be neglected; indeed they are part of the challenges to delaminate this interface at all. We found energy release rates increasing with fracture mode mix, and such values close to pure tensile opening at the crack tip. We recommend to exclude data from short crack lengths and to carefully expose the sample flanks. The results promise to extend the available interfacial fracture data soon.