Hélène Fremont
University of Bordeaux
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Publication
Featured researches published by Hélène Fremont.
Microelectronics Reliability | 2000
M.G. Périchaud; Jean-Yves Deletage; Hélène Fremont; Y. Danto; C. Faure
Abstract This paper compares the efficiency of two thermosetting and one thermoplastic conductive adhesives for surface mount technology (SMT) assemblies. Their reliability is evaluated during accelerated life tests through electrical and mechanical measurements. Contact metallizations are taken into account. Finite element simulations confirm the experimental results, and a parametric study permits us to define some choice criteria for the physical properties of adhesives.
Microelectronics Reliability | 2009
Maxime Berthou; P. Retailleau; Hélène Fremont; Alexandrine Guédon-Gracia; C. Jéphos-Davennel
Abstract This paper describes a reliable and reproducible method to reveal the microstructure of lead-free solder joints. This method is then used to follow the aging of lead free assembled chip resistors and BGA, with either ENIG or immersion Sn finishes. Two types of aging were applied: accelerated thermal cycles (ATC), and iso-thermal storage at three different temperatures. The associated failure mechanisms are compared and discussed. During ATC, microstructural changes under thermo-mechanical fatigue are evidenced, whereas thermal storage only induces intermetallic evolution, depending on the finish type.
Microelectronics Reliability | 2006
W.C. Maia Filho; M. Brizoux; Hélène Fremont; Yves Danto
The current trends in electronics are towards high frequency signal operation, higher interconnects density and continuous reliability improvement interconnects. In order to characterize reliability, accelerated reliability tests are applied to evaluate lifetime and to determine acceptable reliability levels. Based on this fact, the definition of failure criteria is fundamental to ensure repeatability and high confidence level of test results. Accelerated tests normally use special daisy chain components to allow in-situ electrical continuity measurements. Electrical continuity is used as an indicator of second level interconnect integrity. Industrial standards, IPC for example (IPC-SM-785, 1992), recommend the use of high sampling rate event detectors and establish failure criteria. The reason is that intermittent failures can appear long time before permanent open circuits (Brizoux et al., 2002). The approach presented in this paper is meant to improve the understanding of intermittent failure and to determine the appropriate failure criterion for continuous monitoring test.
Microelectronics Reliability | 2013
J. B. Jullien; Hélène Fremont; Jean-Yves Delétage
Abstract This work describes the thermo-mechanical behaviour of Polyimide Isotropic Conductive Adhesive (ICA) used on passive components assemblies in harsh thermal environment. Shear tests were carried out in an “Instron tensile” machine for thermo-mechanical characterization. The stress–strain curves have been used finite element models (FEM) parameterisation. Numerical modelling simulations have shown the most probable failure area, where accumulated strain in the adhesive is the highest. In addition, simulation results have been compared with results from aged assemblies. The comparative approach has permitted to evaluate the influence of the presence of voids in adhesive joints.
international conference on thermal, mechanical and multi-physics simulation and experiments in microelectronics and microsystems | 2009
Wei Feng; K. Weide-Zaage; Frédéric Verdier; Bernard Plano; Alexandrine Guédon-Gracia; Hélène Fremont
The migration issue of Package-on-Package (PoP) is investigated in this article. The migration phenomenon can be amplified as the density of solder bumps increases, while the paths are very finer as well in PoP.
Microelectronics Reliability | 2007
Kirsten Weide-Zaage; David Dalleau; Yves Danto; Hélène Fremont
In this study the degradation phenomena in dual-damascene copper (DD-Cu) metallizations will be investigated due to high current densities and substrate temperatures by finite element modeling. The static and dynamic simulations and calculations will show the suitability of the method in comparison to experimental results from the literature. Different geometry variations, like overlap and via height as well as a variation of the stress free temperature of the metallization will be carried out. It will be found, that if the maximum temperature in the metallization is near the stress free temperature the electromigration is dominant. If the temperatures differ from the stress free level stress migration will be predominant. Out of this it will be found that the knowledge of the stress free temperature in the metallization is very important for a sufficient migration determination.
international conference on thermal, mechanical and multi-physics simulation and experiments in microelectronics and microsystems | 2010
Samed Barnat; Hélène Fremont; Alexandrine Gracia; Eric Cadalen; Catherine Bunel; François Neuilly; Jean-René Tenailleau
Increasing demand, regarding to advanced 3D packages and high performance applications, accelerates the development of 3D silicon integrated circuit, with the aim to miniaturize and reduce cost. The study of the reliability of the through silicon via and of most critical areas for the emergence of failure remains a major concern. This paper deals with the variation of stress and strain induced in a through silicon via. It exhibits different recommendations to improve the reliability through a screening of influential parameters. These studies are focused on a single Through Silicon Via (TSV). The stress and strain induced in a TSV depends on different materials and geometrical parameters. Simulation results of accumulated stress and plastic strain show that the interface between copper and silicon is an indicator for a potential failure such as delamination and die cracking. The stress in the TSV also depends on the variation of copper filling, the size of holes and the thickness of wafers. Increasing via diameter increases the stress in the TSV and the effect of thermal expansion mismatch between copper, silicon and silica.
international conference on electronic packaging technology | 2008
Xiaosong Ma; K.M.B. Jansen; L.J. Ernst; W.D. van Driel; O. van der Sluis; G.Q. Zhang; Charles Regard; Christian Gautier; Hélène Fremont
The use of the non-hermetic material for electronic packaging does raise a potential concern, i.e. moisture induced interfacial delamination and pop corning during reflow. Therefore, it is very important we can correctly model the moisture absorption property. In this study, moisture absorption and desorption properties of three kinds of package materials were investigated. Moisture absorption equilibrium weight gain and diffusion coefficient at different temperature and different humidity are characterized. Moisture absorption processes are simulated using a 3D model at conditions according to the moisture sensitivity test levels. Finally moisture absorption is verified by our research carrier.
Microelectronics Reliability | 2007
Manoubi Auguste Bahi; Pascal Lecuyer; Hélène Fremont; Jean-Pierre Landesman
Abstract The purpose is to create a new qualification methodology for plastic encapsulated electronic components used in an automotive environment at high temperature. It is based on the acceleration of failure mechanisms like ball bond lift (due to intermetallic Au–Al thickness growth), by combination of environmental stresses. The delamination measurement was used as an indicator of potential assembly weaknesses. An optimized package sequential qualification test flow is proposed.
Microelectronics Reliability | 2012
Lutz Meinshausen; Hélène Fremont; Kirsten Weide-Zaage
Abstract Because of material movements intermetallic compound layers are formed between metal layers and solder joints. These intermetallics affect the reliability of the solder joints by reducing their lifetime during drop test or by accelerating the migration induced void formation. This study investigates the migration kinetics of Cu, Ni, Au and Sn in SAC305 solder joints on three different metal layers: Cu, NiAu and NiP. The aim of this study is the identification and description of migration processes during aging of solder joints with one and double sided Ni diffusion barriers.