Yves Danto

Kink effect in HEMT structures: A trap-related semi-quantitative model and an empirical approach for spice simulation

Abstract The mechanism of kink effect in AlGaAs/GaAs high-electron-mobility transistors (conventional, normally-on) is reported. An analytical model, in good agreement with experimental results (behaviour of the kink voltage with temperature and gate voltage) shows that this effect is related to impact ionization phenomenon. Accurate prediction of the I − V characteristics including the kink effect can be carried out, extending the d.c.-equations of the SPICE GaAs-FET model. Three parameters are used in the kink region for the drain current. All of them are extracted from experimentally measured I − V characteristics and preserve physical meaning.

High temperature reliability testing of aluminum and tantalum electrolytic capacitors

Abstract Nowadays, many innovations in the automobile are enabled by electronics. Ambient requirements can be very stringent especially when the temperature reaches 150 °C or even more. Especially electrolytic capacitors are known to be critical devices at high temperatures. Therefore, it is necessary to validate the performance of such components and check their reliability during high temperature operation. In this paper we discuss how to predict the lifetime of both aluminum and tantalum electrolytic capacitors. In that aim we first review state of the art qualification tests that allow a life prediction. We describe a test setup that we have built in order to investigate electrolytic capacitors by LCR and leakage current measurements at temperatures above current manufacturers specifications. Results for different capacitors after variation of tests conditions will be presented.

Improvement of aging simulation of electronic circuits using behavioral modeling

This paper presents an original method of analog circuits aging simulation. This method is based on a behavioral modelling of circuits that includes the effects of degradations on circuit parameters, on the basis of transistors aging. The efficiency of the method is demonstrated in the case of hot carriers degradation in an amplifier

Improved physical understanding of intermittent failure in continuous monitoring method

The current trends in electronics are towards high frequency signal operation, higher interconnects density and continuous reliability improvement interconnects. In order to characterize reliability, accelerated reliability tests are applied to evaluate lifetime and to determine acceptable reliability levels. Based on this fact, the definition of failure criteria is fundamental to ensure repeatability and high confidence level of test results. Accelerated tests normally use special daisy chain components to allow in-situ electrical continuity measurements. Electrical continuity is used as an indicator of second level interconnect integrity. Industrial standards, IPC for example (IPC-SM-785, 1992), recommend the use of high sampling rate event detectors and establish failure criteria. The reason is that intermittent failures can appear long time before permanent open circuits (Brizoux et al., 2002). The approach presented in this paper is meant to improve the understanding of intermittent failure and to determine the appropriate failure criterion for continuous monitoring test.

Real measures, virtual instruments

This paper presents the realisation of a remote lab on a European scale. The involved countries are France, Germany, and Spain. The architecture of the lab is described and the functionality has been tested. It concerns the instrumentation in the field of microelectronics. It has been applied to the characterisation of MOS transistors.

Dynamic void formation in a DD-copper-structure with different metallization geometry

In this study the degradation phenomena in dual-damascene copper (DD-Cu) metallizations will be investigated due to high current densities and substrate temperatures by finite element modeling. The static and dynamic simulations and calculations will show the suitability of the method in comparison to experimental results from the literature. Different geometry variations, like overlap and via height as well as a variation of the stress free temperature of the metallization will be carried out. It will be found, that if the maximum temperature in the metallization is near the stress free temperature the electromigration is dominant. If the temperatures differ from the stress free level stress migration will be predominant. Out of this it will be found that the knowledge of the stress free temperature in the metallization is very important for a sufficient migration determination.

Vibration lifetime modelling of PCB assemblies using steinberg model

Abstract Automotive requirements are nowadays not only limited to high temperatures but more and more demands are driven towards vibration and higher acceleration values due to the direct mounting of the Electronic Control Units on the Engine. Temperature cycle testing and combined testing methods have been under study for a long time but literature concerning Vibration Modelling is very poor in comparison with thermal models like Arrhenius or thermo-mechanical based models like Coffin-Manson. In this article, a revisit of the Steinberg Model is presented with a direct application on tantalum capacitors populated boards. Experimental results with various sinusoidal excitation g-level are presented; whereas on the other side FEM simulations are performed and results are implemented in the Steinberg Model, in order to identify model parameters.

An improved method for automatic detection and location of defects in electronic components using scanning ultrasonic microscopy

The paper deals with a method for the automatic analysis and characterization of defects due to encapsulation or/and surface mount processes of microelectronic devices. This method is based on digital signal processing of ultrasonic signals in the 10-100 MHz frequency range and in particular used for automatic evaluation of time-of-flight between echoes received by the acoustic transducer. The signals are firstly preprocessed by a new algorithm, based on the Wiener filtering, and then by a numeric algorithm, based on the wavelet transform, already applied successfully to this problem. The preprocessing phase increases the sensitivity of successive numeric algorithm. The theory underlying the preprocessor and the chosen procedure to implement it are described in detail. Furthermore, experimental results obtained applying the proposed method on acoustic signals from an electronic structure acquired through an ultrasonic scanning system are given and discussed.

Localization of defects in die-attach assembly by continuous wavelet transform using scanning acoustic microscopy

Abstract The main goal of this paper is to describe a new method based on Continuous Wavelet Transform (CWT) algorithm and successfully implemented in a Scanning Acoustic Microscope, developed at IXL Laboratory, for the measurement of Time Of Flight (TOF) between ultrasonic echoes and contribute to the help of defect diagnosis and failure analysis of a die-attach assembly. The paper is divided into three main parts. After a brief description of the different methods for the TOF measurement, we give the strong interest to use Wavelet Transform due to the nature of ultrasonic signals. The principle of the CWT algorithm and the TOF measurement method associated are explained. The robustness of the CWT algorithm is evaluated to achieve information concerning its performances in presence of different signal parameters and SNR with a statistical treatment. 1n final, we propose an application of this algorithm to the help of acoustic images interpretation. This application concerns the detection and localization of defects into a die-attach assembly, specially the detection of fine crack.

Non-destructive detection and localization of defects in multilayer ceramic chip capacitors using electromechanical resonances

High reliability multilayer ceramic chip capacitors are necessary for use in surface mounting processes which are more mechanically and thermally severe than the traditional through-hole processes. Moreover, in specific environments, even a small defect can be considered as catastrophic for the working of the electronic circuit or even of the entire system. In order to look for the failures—intrinsic latent defects and those caused by SMT soldering processes—appearing in these components, many techniques of analysis can be used. With this present work, we focus on one technique based on the principle of electromechanical resonances existing in piezoelectric materials under a d.c. bias field. The free correlation between the impedance measurement of the chip under a sufficient voltage allows us to highlight some conclusions concerning the behaviour, the nature of the defects and the long-term reliability of ceramic chip capacitors. This method has the advantage of being non-destructive, rapid, efficient and low-cost.