François Marc

Improvement of aging simulation of electronic circuits using behavioral modeling

This paper presents an original method of analog circuits aging simulation. This method is based on a behavioral modelling of circuits that includes the effects of degradations on circuit parameters, on the basis of transistors aging. The efficiency of the method is demonstrated in the case of hot carriers degradation in an amplifier

Preliminary results of storage accelerated aging test on InP/InGaAs DHBT

The reliability of InP/GaAsSb/InP DHBTs designed for very high-speed ICs applications is studied after storage accelerated aging tests performed up to 2000 hours at ambient temperatures of 180, 210 and 240°C. The HiCuM model was used for modelling DC electrical characteristics measured during aging tests. The signature of the major degradation mechanism points out an evolution of the emitter access resistance. The failure mechanism is related to the Au and/or Ti diffusion into InGaAs emitter contact layer. However, the maximum current gain decrease is lower than 7 % after 2000 hours at 240°C. This shows the robustness of the InP/GaAsSb/InP DHBT under test.

Investigation of the degradation mechanisms of InP/InGaAs DHBT under bias stress conditions to achieve electrical aging model for circuit design

Abstract The reliability of InP/InGaAs DHBT under high collector current densities and low junction temperatures is analyzed and modeled. From the Gummel characteristics, we observe several types of device degradation, resulting from the long term changes of base and collector current in both lower and higher base–emitter voltage ranges which impacts the reduction of DC current gain. In this paper, we investigate the underlying physical mechanism of base and collector current degradation with the help of TCAD device simulation. We chose the HICUM model level2 for the modeling purpose to evaluate the drift of model parameters according to stress time. The evolution of the model parameters is described with suitable equations to achieve a physics based compact electrical aging model. The aging laws and the parameter evolution equations with stress time are implemented in compact electrical aging model which allows us to simulate the impact of device failure mechanisms on the circuit in operating conditions.

Advancements on reliability-aware analog circuit design

This paper presents a new physics-based method for reliability prediction and modeling of Integrated Circuits (ICs). By implementing transistor degradation mechanisms via differential equations in the transistor compact model, the aging of the circuit can be simulated over (accelerated) time under real conditions. Actually, each transistor in the circuit integrates the voltage, current and temperature stress it suffers which results in (slowly) varying model parameters over time. Due to its straightforward implementation in commercial Computer Aided Design (CAD) flows, this method allows designers creating reliability-aware circuit architectures at an early stage of the design procedure, well before real circuits are actually fabricated. Application examples and results are presented for an InP/InGaAs DHBT process, but the universality of the method makes it suitable also for silicon based technologies such as CMOS and (SiGe) BiCMOS.

Thermal aging model of InP/InGaAs/InP DHBT

Abstract This paper presents the measurement result and modeling of the storage accelerated aging tests performed on InP/InGaAs/InP DHBT. From the Gummel characteristics, we observe that the principle mode of device degradation results from the increase of base current and reduction in the current gain which comes from the base–emitter junction periphery. Topics covered include: (1) underlying physical mechanism of base current degradation; (2) choosing HICUM model LEVEL2 for the modeling purpose; (3) evolution of model parameters with stress time after the extraction of model parameter before aging and the description of the parameter drift with suitable equation; (4) implementation in compact electrical model allows to simulate the impact of device failure mechanisms on the circuit in operating conditions.

Relation between HCI-induced performance degradation and applications in a RISC processor

Die shrinking combined with the non-ideal scaling of voltage increases the probability of MOS transistors to encounter hot carrier injections (HCI). This failure mechanism causes a performance degradation of digital ICs. The evaluation of timing degradations becomes a must-have to ensure the expected time-to-market and IC lifetime early in the design flow. In this paper, we present a design/verification flow at front-end from which we accurately analyze the impact of instruction-set architecture on processor timings. We show results on a RISC processor named AntX and designed in a 40 nm TSMC technology. Using typical-case scenarios can increase the maximum operating frequency by 15% on average compared to a worst-case scenario, while considering the same lifetime. We also identify that the shift operations cause the highest timing degradations along the long processor paths.

High Level Power and Energy Exploration Using ArchC

With the increase in the design complexity of MPSoC architectures, estimating power consumption is very complex and time consuming at lower level of abstraction. We propose a methodology using ArchC named Power-ArchC for a fast high-level estimation of processor power consumption. Power values are obtained by an instruction level power characterization at gate level. The requirements for power evaluation infrastructure are compatible processor models written in ArchC and RTL, and the Technology library. We show power results for a 32-bit MIPS processor with different benchmarks, based on 45nm technology.

Fault and diagnosis on a successive approximation ADC

In successive approximation A/D converters, the origin of failure is located through the bit error which is computed from the histogram, if it fulfil some conditions. In this paper, we present the real case of a failing A/D converter whose bit error is not computable. Consequently, the failure localization is performed using an alternative methodology including external electrical characterization and electron beam testing (EBT).

A general methodology using an electron beam tester applied to failure localization inside a logic integrated circuit

An analytical methodology for failure localization inside logical integrated circuits (ICs) based on an electron beam tester is presented. It consists of the splitting of every objective into simpler ones associated with a rigorous choice of the observation technique and of the applied electrical sequences. The choice depends on the IC, the physical parasitic phenomena and the wished goal. The efficiency and the quickness of the methodology is demonstrated by a real case analysis.

Submicrometer InP/InGaAs DHBT Architecture Enhancements Targeting Reliability Improvements

We report on the reliability of InP/InGaAs DHBTs used in very high speed ICs and present the analysis of HBT failure mechanisms after thermal and bias stresses (junction temperature from 87°C to 240°C, collector current density fixed at 400 kA/cm2, and collector-emitter voltage from 1.5 to 2.7 V). The physical origins of these failure mechanisms have been investigated using TCAD simulation. It points out the emitter sidewalls, the base-emitter junction periphery, and the emitter access resistance. Through three device generations, the analysis pointed out the successive technological enhancements to reduce the thermal resistance RTH and subsequently decrease the self-heating, leading to minimizing the impact of failure mechanisms.