Hemanta Kumar Mondal

An energy efficient wireless Network-on-Chip using power-gated transceivers

Networks-on-Chip (NoCs) have been accepted as scalable and efficient communication backbone for many-core Systems-on-Chip (SoCs) by both the academia and the industry. However, the traditional approaches of implementing a NoC with planar metal interconnects have high latency and significant power consumption overhead. This is mainly due to the multi-hop links used in data exchange, specifically when the number of cores is significantly high. To address these problems, multi-hop wire interconnects in a NoC can be replaced with high-bandwidth single-hop long-range wireless links. This opens up new opportunities for detailed investigations into the energy efficient design of wireless NoCs using suitable on-chip wireless transceivers. Wireless transceivers with power gating can significantly improve the energy efficiency of the network. In this paper, we have implemented and evaluated sleep transistor based power-gated transceiver along with power-gating controlling unit for low power on-chip wireless interconnects. Design considerations for augmenting this technique with different wireless NoC architectures and corresponding overheads are also presented.

Power efficient router architecture for wireless Network-on-Chip

Wireless Networks-on-Chip (WNoCs) offer the most promising solution to overcome limitations of conventional Networks-on-Chip (NoCs) for long distance communications in future many-core processors. Detailed investigations of NoC with wireless interfaces (WIs) highlight their many benefits. But, static power consumption associated with WI components and routers, in general, is considerably high. By selectively turning off unused/ rarely used routers, static power consumption can be reduced. Additionally, in WNoCs with broadcast-capable antennas, only a single active wireless communication is allowed and many WIs remain inactive for longer duration and dissipate static power. To avoid this, we propose power-efficient fine-grained router architecture (FGRA) to keep power consumption to minimum. We also minimize wake-up latency by using an approach to wake-up a power-gated transceiver whenever signal is detected at its receiving antenna. We also propose non-blocking bypass channel (NBBC) to bypass power-gated routers and minimize routing latency and contention. We evaluate our proposed router design in presence of real and synthetic traffic patterns. FGRA saves up to 88.76% (per base router) and 62.50% (per WI) of static power as compared to regular architecture with 2.42% area overhead. Based on the utilization, FGRA also reduces overall network power consumption by 37.20% on average with negligible performance degradation. Design considerations for augmenting existing NoCs with these power-gated routers and corresponding overheads are also presented.

An Efficient Hardware Implementation of DVFS in Multi-core System with Wireless Network-on-Chip

Networks-on-Chip (NoC) have emerged as communication backbones for enabling high degree of integration in future many-core chips. Despite their advantages, the communication is multi-hop and causes high latency and power dissipation, especially in larger systems. Wireless Network-on-Chip (WNoC) significantly improves the latency over traditional wired NoCs for multi-core systems. But on-chip wireless interfaces (WIs) have their own power and area overhead. In this paper we design and implement a Dynamic Voltage Frequency Scaling (DVFS) technique and extend it to provide power gating to the WIs. This approach effectively reduces the energy consumption in multi core systems. A centralized controller with dual-band wireless transceiver implements per-core DVFS. The scheme ensures balanced workload and energy consumption of the chip and efficient power gating for the WIs. It helps to alleviate the power consumption up to 33.085 % for on-chip communications infrastructure with little overheads.

Interference-Aware Wireless Network-on-Chip Architecture Using Directional Antennas

Wireless Network-on-Chip (WiNoC) has been recently introduced for addressing the scalability limitations of conventional multi-hop NoC architectures. Existing WiNoC architectures generally use millimeter-wave antennas without significant directional gains, along with token passing protocol to access the shared wireless medium. This limits the achievable performance benefits since only one wireless pair can communicate at a time. It is also not practical in the immediate future to arbitrarily scale up the number of non-overlapping channels by designing transceivers operating in disjoint frequency bands in the millimeter-wave spectrum commonly adopted for on-chip wireless interconnects. Consequently, we explore the use of directional antennas whereby multiple wireless interconnect pairs can communicate simultaneously. However, concurrent wireless communications can result in interference. This can be minimized in NoC by optimal placement of wireless interfaces (WIs) to maximize performance while minimizing interference. To address this, we propose an interference-aware WIs placement algorithm with routing strategy for WiNoC architecture by incorporating directional planar log-periodic antennas (PLPAs). This directional wireless network-on-chip (DWiNoC) architecture enables point-to-point links between transceivers and hence multiple wireless links can operate at the same time without interference.

Energy efficient on-chip wireless interconnects with sleepy transceivers

Both industry and academia has accepted Networks-on-Chip (NoCs) as the communication backbone for multi-core Systems-on-Chip (SoCs). But the traditional approach of implementing a NoC with planar metal interconnects has high latency and significant power consumption overhead. This is due to multi-hop links used in data exchange, specifically when the number of cores is significantly high. To address these problems multi-hop wire interconnects in a NoC can be replaced with high-bandwidth single-hop long-range wireless links. This opens up new opportunities for detailed investigations into the energy efficient design of wireless NoCs using suitable on-chip wireless transceivers. Wireless transceivers with power gating can significantly improve the energy efficiency of the interconnection network. In this paper we have implemented and evaluated sleep transistor based power-gated transceiver for low power on-chip wireless interconnects. This approach improved power saving for wireless communication up to 70% compared to existing wireless NoC. The transceiver consumes 36.8771 mA current while on and less than 9 nA while in sleep mode from 1 V power supply. The delay associated with this wireless transceiver is less than 10 ps.

Adaptive multi-voltage scaling in wireless NoC for high performance low power applications

Networks-on-Chip (NoCs) have garnered significant interest as communication backbone for multicore processors used across a wide range of fields that demand higher computation capability. Wireless NoCs (WNoCs) by augmenting single hop, long range wireless links with wired interconnects; offer the most promising solution to reduce multi-hop long distance communication bottlenecks and opens up innumerable possibilities of topological innovations that are not possible otherwise. However, energy consumption in routers along with Wireless Interface (WI) components still remains considerably high. Specifically for large systems with many nodes in the network, a significant amount of energy is consumed by the communication infrastructure (routers, links, WIs). The usage of the routers and WIs are application dependent and for most cases performance requirements can be met without operating the whole communication infrastructure to its maximum limit. Dynamic reconfigurable systems that can switch between both high performance and low power modes can cater to wide range of applications. In this paper, we propose a novel design methodology for energy efficient WNoC using Adaptive Multi-voltage Scaling (AMS) that reduces dynamic power consumption, along with power gating to prevent static power dissipation in routers and WIs. We evaluate our proposed design in presence of real and synthetic traffic patterns. This approach saves up to 62.50% of static power with less than 1% area overhead. In different traffic scenarios, the proposed WNoC reduces overall packet energy dissipation up to 35% on average compared to a regular WNoC, without significant performance degradation. Design considerations for augmenting existing WNoCs with these routers and corresponding overheads are also presented.

A Hardware and Thermal Analysis of DVFS in a Multi-core System with Hybrid WNoC Architecture

Evolution of CMOS manufacturing technologies has led to billions of transistors per chip, many core and System-on-Chip (SoC) realizations in current day systems. But maintaining this trend is a significant challenge due to the power and thermal issues. As the devices are scaled and number of transistors on the chip increases, the power density across the chip increases rapidly with each generation. This further results in increased system temperature that can cause damage to the system. Dynamic Voltage/Frequency Scaling (DVFS) schemes reduce the power consumption without significant loss in system performance. In this paper, we design and evaluate a centralized DVFS control mechanism for multi core systems and discuss its merits and overheads. One of the major issues with centralized controller implementation is the long delays associated with signal transmission between the controller and different clusters in the system. To alleviate this issue, we use wireless interfaces for transmitting controller signals along with the data signals. Towards this goal, we design a dual band transceiver & antenna for the wireless interfaces and present their implementation details. Finally the thermal profile of the proposed DVFS mechanism is analyzed and compared with normal operating conditions.

Energy-Efficient Transceiver for Wireless NoC

Network-on-Chip (NoC) with wireless interconnects is one of the potential solutions to overcome limitations of conventional NoC architectures over far-apart communications in multicore systems. Detailed investigations of Wireless NoC (WNoC) highlight their many benefits. But, idle-state power consumption associated with WI interfaces and routers is significantly high. To reduce the idle-state power consumption, a power gating technique can be incorporated with WNoC architectures. However, power gating can lead to adverse effects like IR drop, short-term sleep/wake up that increase the transient energy consumption specially for burst traffic, and also increases the cumulative settling time to get exact output response from the power gated components. To address these problems, we propose an energy-efficient transceiver for WNoC architecture using power gating. In this paper, we also present the details of techniques that minimizes the impact of power gating on performance. Proposed architecture saves up to 62.50% of idle-state power of WI as compared with traditional WNoC with minimum impacts of power gating method. This saves the overall packet energy on average by 49% compared to regular WNoC. Design considerations for augmenting power gating in WNoC and corresponding overheads are also presented.

Wireless network-on-chip: a new era in multi-core chip design

The Network-on-Chip (NoC) is an enabling technology to integrate large numbers of embedded cores on a single die. The existing method of implementing a NoC with planar metal interconnects is deficient due to high latency and significant power consumption arising out of multi-hop links used in data exchange. To address these problems multi-hop wire interconnects in a NoC can be replaced with high-bandwidth single-hop long-range wireless links. This opens up new opportunities for detailed investigations into the design of wireless NoCs (WiNoCs) with on-chip antennas, suitable transceivers and routers. Moreover, as it is an emerging technology, the on-chip wireless links also need to overcome significant challenges pertaining to reliable integration. In this paper we present various challenges and emerging solutions regarding the design of an efficient and reliable WiNoC architecture.

Power- and performance-aware fine-grained reconfigurable router architecture for NoC

Networks-on-Chip (NoCs) have been well accepted for energy efficient on-chip communications for multicore systems. But, a NoC router consumes considerable leakage power even when not in use. For large scale systems, number of unused routers at any time is reasonably high. A significant amount of this leakage power can be saved by applying fine-grained power-gating to unused routers in a NoC. In this paper, we propose fine-grained reconfigurable router architecture (FGRRA) for energy efficient on-chip communications. We also propose strategies to avoid situations where power-gated routers (PGRs) block forward path during packet transfer or isolate a destination router. This is achieved by using additional channels referred as non-blocking bypass channels (NBBC). We evaluate our proposed router design in presence of real and synthetic traffic patterns. FGRRA saves up to 88.76% of leakage power with 2.42% area overhead as compared with baseline router. Based on the utilization, FGRRA also reduces the total network power consumption by 36.18% on average without significant performance degradation. Design considerations for augmenting existing power-gated routers with this technique and corresponding overheads are also presented.