Sujay Deb

Scalable Hybrid Wireless Network-on-Chip Architectures for Multicore Systems

Multicore platforms are emerging trends in the design of System-on-Chips (SoCs). Interconnect fabrics for these multicore SoCs play a crucial role in achieving the target performance. The Network-on-Chip (NoC) paradigm has been proposed as a promising solution for designing the interconnect fabric of multicore SoCs. But the performance requirements of NoC infrastructures in future technology nodes cannot be met by relying only on material innovation with traditional scaling. The continuing demand for low-power and high-speed interconnects with technology scaling necessitates looking beyond the conventional planar metal/dielectric-based interconnect infrastructures. Among different possible alternatives, the on-chip wireless communication network is envisioned as a revolutionary methodology, capable of bringing significant performance gains for multicore SoCs. Wireless NoCs (WiNoCs) can be designed by using miniaturized on-chip antennas as an enabling technology. In this paper, we present design methodologies and technology requirements for scalable WiNoC architectures and evaluate their performance. It is demonstrated that WiNoCs outperform their wired counterparts in terms of network throughput and latency, and that energy dissipation improves by orders of magnitude. The performance of the proposed WiNoC is evaluated in presence of various traffic patterns and also compared with other emerging alternative NoCs.

Wireless NoC as Interconnection Backbone for Multicore Chips: Promises and Challenges

Current commercial systems-on-chips (SoCs) designs integrate an increasingly large number of predesigned cores and their number is predicted to increase significantly in the near future. For example, molecular-scale computing promises single or even multiple order-of-magnitude improvements in device densities. The network-on-chip (NoC) is an enabling technology for integration of large numbers of embedded cores on a single die. The existing method of implementing a NoC with planar metal interconnects is deficient due to high latency and significant power consumption arising out of long multi-hop links used in data exchange. The latency, power consumption and interconnect routing problems of conventional NoCs can be addressed by replacing or augmenting multi-hop wired paths with high-bandwidth single-hop long-range wireless links. This opens up new opportunities for detailed investigations into the design of wireless NoCs (WiNoCs) with on-chip antennas, suitable transceivers and routers. Moreover, as it is an emerging technology, the on-chip wireless links also need to overcome significant challenges pertaining to reliable integration. In this paper, we present various challenges and emerging solutions regarding the design of an efficient and reliable WiNoC architecture.

Design of an Energy-Efficient CMOS-Compatible NoC Architecture with Millimeter-Wave Wireless Interconnects

The Network-on-chip (NoC) is an enabling technology to integrate large numbers of embedded cores on a single die. The existing methods of implementing a NoC with planar metal interconnects are deficient due to high latency and significant power consumption arising out of multihop links used in data exchange. To address these problems, we propose design of a hierarchical small-world wireless NoC architecture where the multihop wire interconnects are replaced with high-bandwidth and single-hop long-range wireless shortcuts operating in the millimeter (mm)-wave frequency range. The proposed mm-wave wireless NoC (mWNoC) outperforms the corresponding conventional wireline counterpart in terms of achievable bandwidth and is significantly more energy efficient. The performance improvement is achieved through efficient data routing and optimum placement of wireless hubs. Multiple wireless shortcuts operating simultaneously further enhance the performance, and provide an energy-efficient solution for design of communication infrastructures for multicore chips.

Enhancing performance of network-on-chip architectures with millimeter-wave wireless interconnects

In a traditional Network-on-Chip (NoC), latency and power dissipation increase with system size due to its inherent multi-hop communications. The performance of NoC communication fabrics can be significantly enhanced by introducing long-range, low power, high bandwidth direct links between far apart cores. In this paper a design methodology for a scalable hierarchical NoC with on-chip millimeter (mm)-wave wireless links is proposed. The proposed wireless NoC offers significantly higher throughput and lower energy dissipation compared to its conventional multi-hop wired counterpart. It is also demonstrated that the proposed hierarchical NoC with long range wireless links shows significant performance gains in presence of various application-specific traffic and multicast scenarios.

Performance evaluation and design trade-offs for wireless network-on-chip architectures

Massive levels of integration are making modern multicore chips all pervasive in several domains. High performance, robustness, and energy-efficiency are crucial for the widespread adoption of such platforms. Networks-on-Chip (NoCs) have emerged as communication backbones to enable a high degree of integration in multicore Systems-on-Chip (SoCs). Despite their advantages, an important performance limitation in traditional NoCs arises from planar metal interconnect-based multihop links with high latency and power consumption. This limitation can be addressed by drawing inspiration from the evolution of natural complex networks, which offer great performance-cost trade-offs. Analogous with many natural complex systems, future multicore chips are expected to be hierarchical and heterogeneous in nature as well. In this article we undertake a detailed performance evaluation for hierarchical small-world NoC architectures where the long-range communications links are established through the millimeter-wave wireless communication channels. Through architecture-space exploration in conjunction with novel power-efficient on-chip wireless link design, we demonstrate that it is possible to improve performance of conventional NoC architectures significantly without incurring high area overhead.

A wideband body-enabled millimeter-wave transceiver for wireless Network-on-Chip

A highly energy-efficient on-chip communication network is crucial for the development of future multi-core chips. In this paper, a wideband millimeter-wave (mm-wave) transceiver was designed for the wireless Network-on-Chip (WiNoC) architecture. In order to reduce the power consumption of the transceiver, body-enabled circuit design techniques were implemented: Forward body-bias was used in the low-noise amplifier (LNA) and power amplifier (PA) circuits to lower the threshold voltages, reducing the supply voltage to 0.8 V. For up-and down-conversion mixers, power-hungry transconductance stages were eliminated by feeding the signals directly into the body terminals of the transistors. In addition, a novel feed-forward structure was designed to extend the bandwidth of the LNA at no cost in power consumption. Simulation results showed that the receiver has a double-sideband noise figure of less than 6 dB, and a peak gain of 20.5 dB, while the transmitter has an output P1dB of 0 dBm. The transceiver achieved an overall 3-dB bandwidth of 18 GHz. Compared with our previous design without body-enabled design techniques, the receiver power consumption was reduced by 20.3%.

Design of an efficient NoC architecture using millimeter-wave wireless links

The Network-on-Chip (NoC) is an enabling technology to integrate large numbers of embedded cores on a single die. Traditional multi-core designs based on the NoC paradigm suffer from high latency and power dissipation due to the inherent multi-hop nature of communication. The performance of NoC fabrics can be significantly enhanced by introducing long-range, low power, and high-bandwidth single-hop links between far apart cores. In this paper we present a design methodology and performance evaluation for a hierarchical small-world NoC with on-chip millimeter (mm)-wave wireless channels as long-range communication links. The proposed wireless NoC offers significantly better performance in terms of achievable bandwidth and energy dissipation compared to its conventional multi-hop wired counterpart in both uniform and non-uniform traffic scenarios. The performance improvement is achieved through efficient data routing, an optimum placement of the wireless hubs, and an energy-efficient transceiver design.

CMOS compatible many-core noc architectures with multi-channel millimeter-wave wireless links

Traditional many-core designs based on the Network-on-Chip (NoC) paradigm suffer from high latency and power dissipation as the system size scales up due to their inherent multi-hop communication. NoC performance can be significantly enhanced by introducing long-range, low power, and high-bandwidth single-hop wireless links between far apart cores. This paper presents a design methodology and performance evaluation for a hierarchical small-world NoC with CMOS compatible on-chip millimeter (mm)-wave wireless long-range communication links. The proposed wireless NoC offers significantly higher bandwidth and lower energy dissipation compared to its conventional non-hierarchical wired counterpart in presence of both uniform and non-uniform traffic patterns. The performance improvement is achieved through efficient data routing and optimum placement of wireless hubs. Multiple wireless shortcuts operating simultaneously provide an energy efficient solution for design of many-core communication infrastructures.

Comparative performance evaluation of wireless and optical NoC architectures

Network-on-Chip architectures with various new emerging interconnect technologies offer unprecedented performance gain compared to their more conventional planar metal interconnect-based counterparts. A comparative analysis of these emerging NoCs will provide a better understanding towards adopting them in the mainstream design. This paper compares performance of small-world NoC architectures having wireless and RF links with optical NoCs and presents design trade offs with system size scaling. Our analysis demonstrates that the small-world NoC architecture with THz wireless shortcuts provides the best performance-area overhead trade-off compared to the other NoCs for both uniform and non-uniform traffic across various system sizes.

Cuff-Less Estimation of Blood Pressure Using Pulse Transit Time and Pre-ejection Period

Non-invasive and cuff-less measurement of arterial blood pressure (BP) is desirable for continuous patient monitoring. Among the various possible techniques pulse transit time (PTT) based approach for estimation of BP is the most promising one. But change in BP is reflected both in PTT and pre-ejection period (PEP). We propose to measure PTT using multiple PPG and PPG-ECG combination recorded at two different sites along the same artery and argue that this approach will eliminate a number of assumptions like constant PEP, involved in the most common method of measuring PTT using QRS complex as timing reference. This approach can help in finding an appropriate BP calibration methodology since true PTT can be measured by this technique.