Hendrawan Soeleman

Robust subthreshold logic for ultra-low power operation

Digital subthreshold logic circuits can be used for applications in the ultra-low power end of the design spectrum, where performance is of secondary importance. In this paper, we propose two different subthreshold logic families: 1) variable threshold voltage subthreshold CMOS (VT-Sub-CMOS) and 2) subthreshold dynamic threshold voltage MOS (Sub-DTMOS) logic. Both logic families have comparable power consumption as regular subthreshold CMOS logic (which is up to six orders of magnitude lower than that of normal strong inversion circuit) with superior robustness and tolerance to process and temperature variations than that of regular subthreshold CMOS logic.

Ultra-low power digital subthreshold logic circuits

Numerous efforts in balancing the trade-off between power, area and performance have been done in the medium performance, medium power region of the design spectrum. However, not much study has been done at the two extreme ends of the design spectrum, namely the ultra-low power with acceptable performance at one end (the focus of this paper), and high performance with power within limit at the other. One solution to achieve the ultra-low power requirement is to operate the digital logic gates in the subthreshold region. We analyze both CMOS and Pseudo-NMOS logic families operating in the subthreshold region. We compare the results with CMOS in the normal strong inversion region and with other known low-power logic, namely, energy recovery logic. Our results show an energy per switching reduction of two orders of magnitude for an 8/spl times/8 carry save array multiplier when it is operated in the subthreshold region.

Ultra-low-power DLMS adaptive filter for hearing aid applications

We present an ultra-low-power, delayed least mean square (DLMS) adaptive filter operating in the subthreshold region for hearing aid applications. Subthreshold operation was accomplished by using a parallel architecture with pseudo nMOS logic style. The parallel architecture enabled us to operate the system at a lower clock rate and reduced supply voltage while maintaining the same throughput. Pseudo nMOS logic operating in the subthreshold region (subpseudo nMOS) provided better power-delay product than subthreshold CMOS (sub-CMOS) logic. Simulation results show that the DLMS adaptive filter can operate at 22 kHz using a 400-mV supply voltage to achieve 91% improvement in power compared to a nonparallel, CMOS implementation. To validate the robust operation of subthreshold logics, a 0.35 /spl mu/m, 23.1 kHz, 21.4 nW, 8/spl times/8 carry save array multiplier test chip was fabricated where an adaptive body biasing scheme is used for compensating process, supply and temperature variations. The test chip showed stable operation at a supply voltage of 0.30 V, which is even lower than the threshold voltages of the pMOS (0.82 V) and nMOS (0.67 V) transistors.

Digital CMOS logic operation in the sub-threshold region

Numerous efforts in balancing the trade-off between power, area and performance have been carried out in the medium performance, medium power region of the design spectrum. However, not much study has been done at the two extreme ends of the design spectrum, namely, the ultra-low power with acceptable performance at one end, and high performance with power within limit at the other. In this paper, we focus on the ultra-low power end of the spectrum where performance is of secondary importance. One solution to achieve the ultra-low power requirement is to operate the digital logic gates in sub-threshold region. In this paper, we analyze both CMOS and Pseudo-NMOS logic operating in sub-threshold region. We compare the results with CMOS in normal strong inversion region and with other known low-power logic, namely, energy recovery logic. Results show energy/switching reduction of two orders of magnitude from an 8×8 carry-save array multiplier when it is operated in the sub-threshold region.

Sub-Domino logic: ultra-low power dynamic sub-threshold digital logic

Sub-threshold static and ratioed logic have recently been proposed to satisfy the ultra-low power requirement in applications such as hearing aids, pace-makers, wearable wrist-watch computers etc. These logic circuits, however, can be operated only at lower frequencies due to lower supply voltage. To increase the frequency of operation, we propose sub-threshold dynamic logic: Sub-Domino logic. A standard full-adder circuit is implemented in both Sub-Domino and Sub-CMOS logic operating in the subthreshold region. Simulation results show that Sub-Domino logic has lower power consumption, smaller area (60% of Sub-CMOS logic), and is 3 times faster than Sub-CMOS logic. It is also shown that Sub-Domino logic has excellent noise margin.

Estimating circuit activity in combinational CMOS digital circuits

Largely because of the recent trend toward portable computing and wireless communication systems, estimating power consumption has become a major concern in todays VLSI circuit and system design. Moreover, the dramatic decrease in feature size, combined with the corresponding increase in the number of devices on a chip, makes the power density larger. To be practical, a portable system should be able to operate for an extended period without requiring a batter recharge or replacement. Achieving this objective means minimizing power consumption. Fast and accurate probabilistic and statistical techniques for estimating circuit activity in CMOS digital circuits offer an alternative to circuit simulation. The techniques use statistics of input signals to determine accurate switching information.

I/sub DD/ waveforms analysis for testing of domino and low voltage static CMOS circuits

This paper describes a test method which relies on the actual observation of supply current (I/sub DD/) waveforms. The method can be used to supplement the standard I/sub DDQ/ test method and it can be easily applied to dynamic and low V/sub DD/, low V/sub T/ CMOS circuits. The method allows us to detect faults which may not be detected by I/sub DDQ/ test methods, and is sensitive enough to detect potential faults, which do not manifest themselves as functional errors. A simple built-in current sensor, which proves to be adequate in verifying the feasibility of using the I/sub DD/ waveforms analysis is proposed to safely observe the current waveforms without significantly changing the waveforms.