Tan-Li Chou

Statistical estimation of sequential circuit activity

In this paper, we present a Monte Carlo based technique to estimate signal activity at the internal nodes of sequential logic circuits. The technique takes spatial and temporal correlations of logic signals into consideration. The Monte Carlo based techniques that have been proposed for combinational circuits can not be directly applied to sequential circuits due to the initial transient problem. The proposed approach deals with this problem by gaining insight from Markov chain theory. Experimental results show that the error (%) of estimated activity of individual nodes is within 3% in comparison to that of long run simulation results.

Accurate power estimation of CMOS sequential circuits

The existence of near-closed sets makes the power estimation of sequential circuits more complicated and time consuming. If caution is not taken, the Monte Carlo-based power estimation techniques for sequential circuits can wrongly terminate the simulation with undesired results. In this paper, we have developed a strategy for a statistical power estimation technique to take into account the possible existence of near-closed sets. We propose an algorithm that partitions states into near-closed sets, if they do exist, and a technique that reduces the computation time of the probabilities of states if state transition graph (STG) is available. If STG is not available, we propose a Monte Carlo-based technique with a warm-up period. The results show that the partitioning algorithm also serves as a detector that signifies whether there may exist near-closed sets. The computation time of state probability can be reduced up to 50% in cases when near-closed sets are present. The relative error of the estimated individual node activity by the Monte Carlo-based technique with a warm-up period is within 3% of the result of long run simulation.

Estimation of activity for static and domino CMOS circuits considering signal correlations and simultaneous switching

This paper presents an accurate estimation of signal activity at the internal and output nodes of static and domino CMOS combinational logic circuits. The methodology is based on a stochastic model of logic signals and takes correlations and simultaneous switching of signals at logic gate inputs into consideration. In static combinational logic synthesis, in order to minimize spurious transitions due to finite propagation delays, it is crucial to balance all signal paths and to reduce the logic depth. As a result of balancing delays through different paths, the inputs to logic gates may switch at approximately the same time. We have developed and implemented a technique to calculate signal probability and switching activity of static CMOS combinational logic circuits. Experimental results show that if simultaneous switching is not considered, the switching activities at the internal nodes can be off by more than 100% compared to simulation based techniques. In contrast, our technique is on the average within 2% of logic simulation results. On the other hand, domino circuits are free of spurious transitions. Based on the precharge scheme of domino circuits, a technique for estimation of signal activity is presented. The results are within 1% of logic simulation results.

Accurate estimation of power dissipation in CMOS sequential circuits

In this paper we present accurate estimation of signal activity at the internal nodes of sequential logic circuits. An exact method, an approximate method and a Monte Carlo based approach that take spatial and temperature correlations of logic signals into consideration are proposed. The results of the approximate and Monte Carlo based methods are within 5% and 2% of that of long run simulation, respectively.

Estimating circuit activity in combinational CMOS digital circuits

Largely because of the recent trend toward portable computing and wireless communication systems, estimating power consumption has become a major concern in todays VLSI circuit and system design. Moreover, the dramatic decrease in feature size, combined with the corresponding increase in the number of devices on a chip, makes the power density larger. To be practical, a portable system should be able to operate for an extended period without requiring a batter recharge or replacement. Achieving this objective means minimizing power consumption. Fast and accurate probabilistic and statistical techniques for estimating circuit activity in CMOS digital circuits offer an alternative to circuit simulation. The techniques use statistics of input signals to determine accurate switching information.

Design of low power digital systems

With the increasing use of portable computing and wireless communication systems, the power dissipation of digital and analog systems are of increasing concern. However, the design objectives to achieve a certain performance with ultralow power dissipation sometimes have conflicting requirements. In this chapter we will first consider in detail how power is dissipated in CMOS digital circuits, derive power estimation techniques for CMOS digital circuits, and present both hardware and software design considerations for ultra low power dissipation.

Low-power driven logic synthesis using accurate power estimation technique

With the increasing use of portable computing and wireless communication systems, the power dissipation of very large scale integrated (VLSI) circuits is becoming a critical concern. Towards this end we introduce algebraic procedures for node extraction and factorization that target low power consumption in combinational logic circuits. A new cost function is also proposed for the sum-of-products representation of the expressions. This cost function is used to guide the power optimization procedures. The spatial and temporal correlations of signals were taken into account to gain accurate power estimation. The results show that an average of 10% saving was gained in power using logic synthesis with the proposed accurate power estimation technique, compared to area optimized designs. Results also show that the power dissipation of the circuit, synthesized assuming temporally uncorrelated primary inputs, can dissipate 75% more power than that of the circuits assuming temporally correlated inputs.