Heng-Ming Hsu

Analytical formula for inductance of metal of various widths in spiral inductors

This paper presents an analytical formula for the inductance of an inductor with the layout of variable metal width, based on the quasistatic approximation. Experimental results indicate that the analytical formula is feasible. A layout with metal whose width increases monotonously from the inner turn has a higher Q value than other configurations of the metal with the same inductance. This information will be of help in designing high-performance inductors for RF integrated circuit applications.

A 0.18 /spl mu/m foundry RF CMOS technology with 70 GHz F/sub t/ for single chip system solutions

This paper presents a high performance RF CMOS technology with a complete portfolio of RF and base band components for single-chip systems. Using optimized CMOS topology and deep n-well isolation, we obtain a F/sub t/ of 60 GHz and F/sub max/ of 55 GHz at 10 mA, a F/sub t/ of 70 GHz and F/sub max/ of 58 GHz at maximum-transconductance bias, and minimum noise figure of 1.5 dB without ground-shielded signal pad. High quality-factor inductors are obtained using Cu interconnect giving a quality factor of 18 at 1.7 nH. MIM capacitors, as well as accumulation and junction varactors are also optimized for enhancing quality factor. For the purpose of eliminating inter-block coupling noise penetrating through substrate, a deep n-well isolation and p-ring have been adopted to suppress the substrate noise by 25 dB and 10 dB respectively. This technology provides a complete solution for single-chip wireless systems.

Modeling and fabrication of a microelectromechanical microwave switch

A microelectromechanical microwave switch manufactured by using a complementary metal oxide semiconductor (CMOS) post-process has been implemented. An equivalent circuit model is proposed to analyze the performance of the microwave switch. The components of the microwave switch consist of a coplanar waveguide (CPW), a suspended membrane and supported springs. The post-process requires only one wet etching to etch the sacrificial layer, and to release the suspended structures. Experimental results show that the switch has an insertion loss of -2dB at 50GHz and an isolation of -15dB at 50GHz. The driving voltage of the switch approximates to 19V.

A Micromachined Microwave Switch Fabricated by the Complementary Metal Oxide Semiconductor Post-Process of Etching Silicon Dioxide

In this study, we investigate the fabrication of a micromachined microwave switch using the commercial 0.35 µm double polysilicon four metal (DPFM) complementary metal oxide semiconductor (CMOS) process and the post-process of only one maskless wet etching. The post-process has merits of easy execution and low cost. The post-process uses an etchant (silox vapox III) to etch the silicon dioxide layer to release the suspended structures of the microwave switch. The microwave switch is a capacitive type that is actuated by an electrostatic force. The components of the microwave switch are coplanar waveguide (CPW) transmission lines, a suspended membrane and supported springs. Experimental results show that the driving voltage of the switch is about 17 V. The switch has an insertion loss of -2.5 dB at 50 GHz and an isolation of -15 dB at 50 GHz.

Improving the RF performance of 0.18 /spl mu/m CMOS with deep n-well implantation

The radio-frequency (RF) figures of merit of 0.18 /spl mu/m complementary metal-oxide-semiconductor (CMOS) technology are investigated by evaluating the unity-current-gain cutoff frequency (F/sub t/) and maximum oscillation frequency (F/sub max/). The device fabricated with an added deep n-well structure is shown to greatly enhance both the cutoff frequency and the maximum oscillation frequency, with negligible DC disturbance. Specifically, an 18% increase in F/sub t/ and 25% increase in F/sub max/ are achieved. Since the deep n-well implant can be easily adopted in a standard CMOS process, the approach appears to be very promising for future CMOS RF applications.

Implementation of high-coupling and broadband transformer in RFCMOS technology

This paper proposes a structure for transformer with high-coupling, broadband, and small chip area characteristics using current silicon-based technology. The proposed device has tight coupling (k=0.92), wide bandwidth (f/sub SR/=30.8 GHz), and minimum chip area (OD=140 /spl mu/m). Furthermore, the analytical formula for calculating mutual inductance is derived in this study; experimental results indicate that the analytical formula is feasible. The proposed transformer will be useful in designing high-performance RF integrated circuits for wireless applications.

Silicon integrated high performance inductors in a 0.18 /spl mu/m CMOS technology for MMIC

This paper presents a complete portfolio of silicon integrated inductors in a 0.18 μm CMOS technology. In addition to inductor design, we also present a complete optimization methodology with associated modeling and key characterization. Our inductor quality factors have been enhanced by optimizing patterned ground shield and taper coils or using copper metallization. The quality-factor peak can further be optimized at an application-specific frequency band with our optimization algorithm. To facilitate IC design with inductors, a novel model considering eddy current loss was developed, Finally, to integrate inductors into a system-chip, inductor-to-inductor and substrate-inductor coupling were investigated.

Investigations of bulk dynamic threshold-voltage MOSFET with 65 GHz "normal-mode" f/sub t/ and 220 GHz "over-drive mode" f/sub t/ for RF applications

The RF properties of bulk dynamic threshold-voltage MOSFET (B-DTMOS) with deep n-well isolation was investigated both under the normal DTMOS mode and two newly-proposed DTMOS operation modes: moderate (0.6 V<V/sub gs/=V/sub bs/<0.85 V) and over-drive (V/sub gs/=V/sub bs/>0.85 V) modes. While f/sub t/ can be improved to 65 GHz at 12.5 mA with 1.5 V V/sub ds/ bias under normal mode DTMOS operation, a high f/sub t/ of 220 GHz with good linearity and stability is achieved under over-drive operation mode.

Design of On-Chip Transformer With Various Coil Widths to Achieve Minimal Metal Resistance

A layout design algorithm of a variable-width transformer is proposed to minimize metal resistance in this letter. The proposed algorithm can rapidly design metal widths in each coil of a planar transformer for a given chip area. Two on-chip transformers with identical self-inductance are fabricated to verify the proposed algorithm in 90-nm CMOS technology. Measurement results demonstrate the improvement of metal resistance approximates to the value of 11.6%. Results of this study provide an effective algorithm to design a minimal-loss transformer for radio frequency integrated circuit applications.

Compact Layout of On-Chip Transformer

This study develops a compact layout for an on-chip transformer with both wide range of turn ratios and a high coupling coefficient in a small chip area. Analytical formulas are applied to calculate the self-inductances in the design stage. Therefore, six devices with various turn ratios are designed to verify the proposed layout. All devices are fabricated using foundry 130 nm complementary metal-oxide semiconductor technology. Measurements reveal that the proposed transformer has a wide range of n values (1-5.68) and high coupling k values (0.99-0.48) for a chip area of 1002 ¿m2.