Heng-Yu Jian

A Low Phase Noise, Wideband and Compact CMOS PLL for Use in a Heterodyne 802.15.3c Transceiver

A low phase noise, wideband, mm-wave, integer-N PLL that is capable of supporting an 802.15.3c heterodyne transceiver is reported. The PLL can generate 6 equally spaced tones from 43.2 GHz to 51.84 GHz, which is suitable for a heterodyne architecture with FLO=(4/5)×FTRX. Phase noise is measured directly at the FLO frequency and is better than -97.5 dBc/Hz@1 MHz across the entire band. The reported frequency synthesizer is smaller, exhibits less phase noise, and consumes less power than prior art. In addition, the FLO tone corresponds to the fundamental of the VCO as opposed to a higher harmonic.

A Fractional- N PLL for Multiband (0.8–6 GHz) Communications Using Binary-Weighted D/A Differentiator and Offset-Frequency Δ-Σ Modulator

A compact, low power and global-mismatch-tolerant 0.8-6 GHz fractional-N PLL is designed to cover IEEE 802.11abg, PCS/DCS and cellular bands. Two new techniques are proposed to cancel the in-band quantization noise and fractional spurs. Firstly, a second order binary-weighted digital/analog differentiator (DAD) is utilized to enable the second order mismatch shaping and reduce the quantization noise by 25 dB, along with advantages of compact circuit implementation with smaller routing area and less power consumption over those of dynamic element matching (DEM) based counterparts. Secondly, mechanisms causing fractional spurs are also identified and a third order offset-frequency delta-sigma (Δ-Σ) modulator is devised to decrease the in-band spurs by 20 dB in simulation and 8 dB in present single-ended circuit implementation.

CMOS THz Generator With Frequency Selective Negative Resistance Tank

This paper reports a CMOS terahertz oscillator with a novel frequency selective negative resistance (FSNR) tank to boost its operating frequency. The demonstrated oscillator can operate at a fundamental frequency of about 0.22 THz, exceeding the CMOS device cutoff frequency of fT. The proposed architecture suppresses undesired 2nd and odd harmonics and boosts the fourth-order harmonic (0.87 THz), which radiates through an on-chip patch antenna. The THz oscillators output spectrum is profiled by using a Michelson interferometer. The oscillator circuit consumes 12 mA from a 1.4 V supply and occupies a 0.045 mm2 die area in a 65 nm CMOS technology.

A

A 70-78-GHz integrated frequency synthesizer is implemented in 65-nm CMOS. It has been integrated in a two-step zero-IF millimeter-wave transceiver for emerging applications, such as 81-86-GHz satellite communication, short-distance high-speed wireless link, as well as imaging and radar. The transceiver utilizes synthesizer voltage-controlled oscillator (VCO) output as the first LORF and 1/8 of LORF as the second LORF to cover the desired frequency band. The proposed synthesizer adopts integer-N architecture with 50-MHz reference. It also features coarse phase rotation to provide beam-forming capability for the intended transceiver. The synthesizer phase noise (PN) has been measured at 1/8 of the VCO frequency, about -102.2 dBc/Hz @ 1-MHz offset, and the measured reference spur for LORF is less than -49 dBc. Thus, the extrapolated PN performance is better than -84 dBc/Hz @ 1 MHz at 70-78 GHz LORF. The embedded frequency synthesizer occupies 0.16-mm2 chip area, including the angular rotator and buffers, and consumes 65 mW under 1-V supply.

{\hbox{70}}{\hbox{–}} {\hbox{78-}}{\hbox{GHz}}

A low phase noise, wideband, mm-wave, integer-N PLL that is capable of supporting a 802.15.3c heterodyne TRX is reported. The PLL can generate 6 equally spaced tones from 43.2GHz to 51.84GHz, which is suitable for a heterodyne architecture with LO=(4/5)RF. Phase noise is measured directly at the LO frequency and is better than −97.5dBc/Hz@1MHz across the entire band. The total power consumption is 72mW from a 1V supply. The reported frequency synthesizer is smaller, exhibits less phase noise, and consumes less power than prior art. In addition, the LO tone corresponds to the fundamental of the VCO as opposed to a higher harmonic. Central to the PLL performance is the design of a low-noise, mm-wave VCO with a 22.9% tuning range. It is noted that resonator nonlinearities may result in significant up-conversion of flicker noise in wideband, mm-wave VCOs. To overcome this, Digitally-Controlled-Artificial-Dielectric (DiCAD) is used to linearize the resonator.

Integrated CMOS Frequency Synthesizer for

An unique time-interleaved dual injection locking scheme has been devised to enable ultra high-speed and low-power frequency division with extended frequency locking range. To prove the concept, two frequency dividers (or prescalers) have been realized in 65nm digital CMOS: one divides continuously from 158GHz to 195GHz (or 21% locking range) with input signal ≪ 0dBm and the other divides from 181GHz to 208GHz (or 14% locking range) with input signal ≪ −1dBm. Both prescalers consume ≪ 2.5mW at 1V supply and contribute negligible phase noise. These test results set the highest F.O.M. (2721 and 2188 GHz2/mW, respectively) for prescalers implemented in any semiconductor technology up to this date, which in both cases is almost 10 times higher than that of prior arts.

W

Terahertz signals have been successfully generated in 65nm CMOS by: 1) stacking a negative-resistance resonator in parallel to the conventional resonant tank to boost the fundamental oscillation to 0.22 THz; and by 2) selectively suppressing the odd and 2nd harmonics to boost the 4th and 6th harmonics in the terahertz regime. Consequently, we have detected 4th and 6th harmonic signals through on-chip antenna radiation at 0.87 and 1.31 THz, respectively, by using a Michelson interferometer. To our best knowledge, this is the first time a signal beyond 1 THz is generated by silicon based semiconductor.

-Band Satellite Communications

To enable CMOS prescaler(s) for submillimeter-wave radio-frequency synthesis, we present a new dynamic frequency divider topology according to a time-interleaved dual-injection locking scheme. Consequently, the prototype prescalers implemented with 65-nm CMOS technology have demonstrated ultra high operation speeds up to 208 GHz, with ultra wide locking range up to 37 GHz, with 2.5-mW power consumption. The achieved performance figure of merit (FOM) [i.e., (speed X range)/power in GHz2/mW] is roughly an order of magnitude higher than that of the state of the art.

A low phase noise, wideband and compact CMOS PLL for use in a heterodyne 802.15.3c TRX

A multibit digital-analog (D/A) differentiator is used in the forward correction path of a dual-truncation delta-sigma (DeltaSigma) D/A converter (DAC) to obtain the desired second-order noise-shaping function for converting mismatch-induced in-band quantization noise to out-of-band frequencies. The multibit D/A differentiator can be configured by embedding binary-weighted current-steering DAC elements into digital differentiators without concern of linearity. In simulations, the newly proposed DeltaSigma DAC is 20 dB more effective in noise reduction than widely adopted first-order noise-shaping methods under the identical mismatch conditions of DAC elements (2% in average global mismatch and 0.3% in adjacent element mismatch). This method also offers advantages of compact circuit implementation with smaller routing area and less power consumption over those of thermometer-coded or digital signal processing based counterparts with the same second-order mismatch shaping.

200GHz CMOS prescalers with extended dividing range via time-interleaved dual injection locking

We present an integrated frequency synthesizer in 65nm CMOS to enable the 81–86GHz satellite communication transceiver. The frequency synthesizer is inserted in a two-step zero-IF millimeter-wave transceiver with LO<inf>RF</inf> at 70–78GHz and LO<inf>IF</inf> at 1/8 of LO<inf>RF</inf> to cover the desired entire frequency bands. It also features coarse phase rotation to endow beam forming capabilities for the intended communication system. The phase noise is ≪ −83dBc/Hz at 1MHz offset as extrapolated from measured value at 1/8 of the VCO frequency (∼9.4GHz). The measured reference spur is ≪−49dBc. Total synthesizer power consumption including LO buffers and phase rotators is 65mW at 1V power supply and the compact layout has rendered small synthesizer core area of 0.16mm².