Mau-Chung Frank Chang

CMP network-on-chip overlaid with multi-band RF-interconnect

In this paper, we explore the use of multi-band radio frequency interconnect (or RF-I) with signal propagation at the speed of light to provide shortcuts in a many core network-on-chip (NoC) mesh topology. We investigate the costs associated with this technology, and examine the latency and bandwidth benefits that it can provide. Assuming a 400 mm2 die, we demonstrate that in exchange for 0.13% of area overhead on the active layer, RF-I can provide an average 13% (max 18%) boost in application performance, corresponding to an average 22% (max 24%) reduction in packet latency. We observe that RF access points may become traffic bottlenecks when many packets try to use the RF at once, and conclude by proposing strategies that adapt RF-I utilization at runtime to actively combat this congestion.

GaAlAs/GaAs heterojunction bipolar transistors: issues and prospects for application

Issues important for the manufacturing of GaAlAs/GaAs heterojunction bipolar transistors (HBTs) and their prospects for application in various areas are discussed. The microwave and digital performance status of HBTs is reviewed. Extrapolated values of maximum frequency of oscillation above 200 GHz and frequency divider operation at 26.9 GHz are reported. Key prospects for further device development are highlighted. >

A CMOS passive mixer with low flicker noise for low-power direct-conversion receiver

A CMOS passive mixer is designed to mitigate the critical flicker noise problem that is frequently encountered in constituting direct-conversion receivers. With a unique single-balanced passive mixer design, the resulted direct-conversion receiver achieves an ultralow flicker-noise corner of 45 kHz, with 6 dB more gain and much lower power and area consumption than the double-balanced counterpart. CMOS switches with a unique bias-shifting network to track the LO DC offset are devised to reduce the second-order intermodulation. Consequently, the mixers IIP2 has been greatly enhanced by almost 21 dB from a traditional single-balanced passive mixer. An insertion compensation method is also implemented for effective dc offset cancellation. Fabricated in 0.18 /spl mu/m CMOS and measured at 5 GHz, this passive mixer obtains 3 dB conversion gain, 39 dBm IIP2, and 5 dBm IIP3 with LO driving at 0 dBm. When the proposed mixer is integrated in a direct-conversion receiver, the receiver achieves 29 dB overall gain and 5.3 dB noise figure.

324GHz CMOS Frequency Generator Using Linear Superposition Technique

This paper presents CMOS for terahertz applications, substantially extended the operation range of deep-submicron CMOS by using a linear superposition method, in which we have realized a 324GHz frequency generator in 90nm digital CMOS with 4GHz tuning range under 1V supply voltage.

A Blocker-Tolerant, Noise-Cancelling Receiver Suitable for Wideband Wireless Applications

A new wideband receiver architecture is proposed that employs two separate passive-mixer-based downconversion paths, which enables noise cancelling, but avoids voltage gain at blocker frequencies. This approach significantly relaxes the trade-off between noise, out-of-band linearity and wideband operation. The resulting prototype in 40 nm is functional from 80 MHz to 2.7 GHz and achieves a 2 dB noise figure, which only degrades to 4.1 dB in the presence of a 0 dBm blocker.

AlGaAs/GaAs heterojunction bipolar transistors fabricated using a self-aligned dual-lift-off process

This paper describes a self-aligned heterojunction-bipolar-transistor (HBT) process based on a simple dual-lift-off method. Transistors with emitter width down to 1.2 µm and base doping up to 1 × 1020/cm3have been fabricated. Extrapolated current gain cutoff frequency ftof 55 GHz and maximum frequency of oscillationf_{\max}of 105 GHz have been obtained. Current-mode-logic (CML) ring oscillators with propagation delays as low as 14.2 ps have been demonstrated. These are record performance results for bipolar transistors. The dual-lift-off process is promising for both millimeter-wave devices and large-scale integrated circuit fabrication.

Terahertz CMOS Frequency Generator Using Linear Superposition Technique

A low Terahertz (324 GHz) frequency generator is realized in 90 nm CMOS by linearly superimposing quadruple (N=4) phase shifted fundamental signals at one fourth of the output frequency (81 GHz). The developed technique minimizes the fundamental, second and third order harmonics without extra filtering and results in a high fundamental-to-4 th harmonic signal conversion ratio of 0.17 or -15.4 dB. The demonstrated prototype produces a calibrated -46 dBm output power when biased at 1 V and 12 mA with 4 GHz tuning range and extrapolated phase noise of -91 dBc/Hz at 10 MHz frequency offset. The linear superposition (LS) technique can be generalized for all even number cases (N=2k, where k=1,2,3,4,...,n) with different tradeoffs in output power and frequency. As CMOS continues to scale, we anticipate the LS N=4 VCO to generate signals beyond 2 Terahertz by using 22 nm CMOS and produce output power up to -1.5 dBm with 1.7% power added efficiency with an LS VCO + Class-B Power Amplifier cascaded circuit architecture.

Heterojunction Bipolar Transistors for Microwave and Millimeter-Wave Integrated Circuits

This paper reviews the present status of GaAIAs/ GaAs HBT technology and projects the impact of these devices on microwave and millimeter-wave integrated circuits. Devices with f/sub max/ above 100 GHz are described. Differential amplifiers are shown to have offset voltages with standard deviation below 2 mV and voltage gain of 200 per stage. Breakdown voltages (BV/sub CBO/) above 20 V are demonstrated. Frequency dividers operating above 20 GHz are described.

Ultrahigh power efficiency operation of common-emitter and common-base HBT's at 10 GHz

The DC and RF characteristics of microwave power HBTs are described. Ultrahigh power-added efficiency is reported for AlGaAs-GaAs HBTs operating at 10 GHz in common-emitter (CE) and common-base (CB) modes. A record high 67.8% power-added efficiency with 11.6 dB associated gain was achieved with a CE HBT at a CW output power of 0.226 W, corresponding to a power density of 5.6 W/mm. With a CB HBT, 62.3% power-added efficiency with 11.85 dB gain and 0.385 W total CW power was demonstrated. Power saturation characteristics of CE and CB HBTs are compared. The importance of bias schemes is discussed. High-efficiency operation in near class B mode is described and compared with FET operation. An advantage of HBT over FET is the low leakage current during the off half cycle in class B operation. Stability conditions for CE and CB HBTs are discussed. >

A blocker-tolerant wideband noise-cancelling receiver with a 2dB noise figure

As narrowband off-chip RF filtering is not compatible with the concept of software-defined radio (SDR), an SDR receiver must be designed to tolerate large out-of-band blockers with minimal gain compression and noise figure degradation. A recent circuit tackles this problem by dispensing with the LNA entirely. This mixer-first approach achieves impressive linearity, but at the expense of noise figure and, since such a receiver has no gain prior to down-conversion, the flicker noise corner can be unacceptably high. Other SDR attempts invariably use a noise-cancelling LNA at the front end, which provides wideband matching, however such approaches have either inadequate linearity or display too large a noise for our purposes. In this work, we propose a hybrid frequency-translational, noise-cancelling (FTNC) receiver that employs two separate down-conversion paths to enable noise cancelling with no voltage gain prior to base-band filtering. The resulting design has a sub-2dB noise figure and tolerates 0dBm blockers with no gain back-off, breaking the traditional noise-linearity trade-off common in all receivers.