Henrik Engseth

Performance Advantages and Design Issues of SQIFs for Microwave Applications

We consider applications of SQIFs as amplifiers for gigahertz frequency range. SQIF-like structures are able to provide much higher dynamic range and linearity than a dc SQUID. We also analyse design limitations imposed by finite coupling inductances and stray capacitances. Possible ways of resolving design issues are discussed.

Influence of the bias supply lines on the performance of RSFQ circuits

Two effects of the bias supply line on the performance of RSFQ circuits have been studied: inductive coupling between the bias supply line and circuit inductances; effect of the mirrored current in the ground plane. The following results of the study are presented: 3D calculations and experimental measurements of inductive coupling between parallel and perpendicular microstrips in presence of one and two ground planes; calculated margins dependence on the external magnetic field in RSFQ cell. Bias current density extraction method has been developed and implemented in RSFQ circuit design flow.

Time-delay optimization of RSFQ cells

This paper presents timing models for RSFQ cells, based on conventional finite-state machines description. Models have been integrated, validated and verified in physical simulations and are suitable for VHDL design. A complete design flow from physical simulation to VHDL simulation, delays optimization, layouting and back-annotation is presented. The correctness of the timing models has been verified in an experiment with 4 /spl times/ 15 shift register.

RSFQ digital signal processor for interference cancellation

RSFQ high performance digital signal processor capable to perform up to 13 13-bit fixed-point GMACS has been designed for use in successive interference canceller in W-CDMA wireless systems. The performance of the processor has been verified by numerical simulations and VHDL simulation using accurate modeling of the RSFQ gates. Components of the processor, 4 /spl times/ 4 and 5 /spl times/ 5 parallel multipliers, 4 /spl times/ 5, 20 /spl times/ 5 and 4 /spl times/ 15 parallel shift registers have been designed and experimentally tested.

New Design of an RSFQ Parallel Multiply-Accumulate Unit

The Multiply-Accumulate Unit (MAC) is a central component of a Successive Interference Canceller, an advanced receiver for W-CDMA base stations. A 4*4 twos complement fixed point RSFQ MAC with rounding to 5 bits has been simulated using VHDL and maximum performance is equal to 24 GMACS (giga multiple-accumulates per second). The clock distribution network has been re-designed from a linear ripple to a binary tree network in order to eliminate data dependence of the clock propagation speed and reduce number of Josephson junctions in clock lines. The 4*4 bits MAC has been designed for the HYPRES 4.5 kA/cm^2 process and its components have been experimentally tested at low frequency: the 5 bit combiner, using an exhaustive test pattern, had margins on DC bias voltage of +-18% and the 4*4 parallel multiplier had margins equal to +-2%.

Miniaturized superconducting microwave filters

In this paper we present methods for miniaturization of superconducting filters. We consider two designs of 7th order bandpass Chebyshev filters based on lumped elements and a novel quasi-lumped element resonators. In both designs the area of the filters, with a central frequency of 2-5 GHz, is less than 1.2 mm2. Such small filters can be readily integrated on one board for multi-channel microwave control of superconducting qubits. The filters have been experimentally tested and the results are compared with simulations. The miniaturization resulted in parasitic coupling between resonators and within each resonator that affected primarily stopband and bandwidth increase. The severity of the error depends on the design in particular, and was less prawn when groundplane was used under the inductances of the resonators. The best performance was reached for the quasi-lumped filter with central frequency of 4.5 GHz, quality factor of 100 and 28 dB stopband.

A high-speed superconducting digital autocorrelator operating at 20.48 GHz

Digital autocorrelators have a number of applications, such as in astronomical observation in the terahertz range, and for spectrum monitoring over wide radiofrequency bands. We have simulated, designed and tested a 16-lag superconducting digital autocorrelator circuits with parallel and also with serial data outputs. By using a novel clock line and a target critical current density of 4.5 kA cm^−2, we have successfully tested this digital circuit up to a clock rate of 20.48 GHz with negligible bit error rates on each lag. Moreover, this autocorrelator design can be expanded with a larger number of lags by tiling chips in a multi-chip module. We also include details of our first multi-chip design.

High Voltage Driver for RSFQ Digital Signal Processor

We present an Rapid Single Flux Quantum (RSFQ) based high voltage driver (HVD) developed for the first amplification stage of a hybrid semiconductor-superconductor memory interface for the RSFQ digital signal processor. Implementation of the driver allows to eliminate the impedance mismatch between RSFQ and standard 50 Omega input of semiconductor electronics and increases the signal-to-noise ratio to reach reliable signal transmission with sufficiently low bit error rate. The driver design is based on the serial stack of 8 SQUIDs with specially configured ground-cuts that form a quasi-coplanar line with 50 Omega impedance. The impedance of the driver has been extracted using 3D EM simulators that accurately take into account multilayer structure and capacitance to the ground. The circuit has been designed for the Hypres 4.5 kA/cm2 process. The driver was simulated numerically in PSCAN. The driver can produce output signal at 1 Gbit/s speed and 2.4 mV signal level that is enough to be sensed by low-noise amplifier on the further amplification stage.

Optimization of high frequency flip-chip interconnects for digital superconducting circuits

This paper presents results of optimization of Multi-Chip-Module (MCM) contact pads and driver circuitry for gigabit chip-to-chip communication. Optimization has been done using 3D Electromagnetic (EM) simulations of flip-chip contacts and time domain simulations of drivers and receivers. A single optimized flip-chip contact has signal refection of less than -20 dB for up to 503 GHz bandwidth. The MCM data link with optimized SFQ driver, receivers and two MCM contact has operational margins on global bias current of +-30% at 30 Gbit/s speed and can operate at maximum 113 Gbit/s of operational speed. High bandwidth transmission requires realization of an advanced flip-chip process with small dimension of contact pads (less 30 micro meter) and small hight of bumps in the order of 2 micro meter. Current processes with about 7 micro meter hight of the bumps requires application of Double Flux Quantum (DFQ) driver. The data link with DFQ driver was also simulated. It has operational margins on global bias current of +-30% at 30 Gbit/s, however the maximum speed of operation is 61 Gbit/s. Several test structures have been designed for measurements signal re°ection, bit error rate (BER) and operational margins of the data link.

Optimization of superconducting microstrip interconnects for rapid single-flux-quantum circuits

In this paper, issues related to the optimization of superconducting passive interconnects are discussed. Results of the microwave optimization of bends, via connections and crossings of superconducting microstrip lines (SMSLs) are reported. The optimum design of the SMSL cross gives more than 95% of transmission and can be well used in a two-bus cross design with up to 14 signal wires. The results have been confirmed by time-domain simulations and measurements.