Irina Kataeva

RSFQ asynchronous serial multiplier and spreading codes generator for multiuser detector

Serial multiplier and serial spreading code generators are vital elements of the RSFQ multiuser detector. We have designed different versions of both circuits to achieve maximum speed and at the same time minimize Josephson junction count. Comparison of different serial multipliers architectures supporting signed multiplication favored for asynchronous shifting over zero circuits based on carry save adder and co-flow distribution of the partial product and the clock. A 25-bit spreading code generator supporting parallel input/output has been designed for 4 kA/cm/sup 2/ (TRW) and for 1 kA/cm/sup 2/ (HYPRES) processes. The corresponding maximum simulated clock speed of 52 GHz and 26 GHz and effective device area of 1/spl times/0.12 mm/sup 2/ and 1.9/spl times/0.2 mm/sup 2/.

Influence of the bias supply lines on the performance of RSFQ circuits

Two effects of the bias supply line on the performance of RSFQ circuits have been studied: inductive coupling between the bias supply line and circuit inductances; effect of the mirrored current in the ground plane. The following results of the study are presented: 3D calculations and experimental measurements of inductive coupling between parallel and perpendicular microstrips in presence of one and two ground planes; calculated margins dependence on the external magnetic field in RSFQ cell. Bias current density extraction method has been developed and implemented in RSFQ circuit design flow.

Time-delay optimization of RSFQ cells

This paper presents timing models for RSFQ cells, based on conventional finite-state machines description. Models have been integrated, validated and verified in physical simulations and are suitable for VHDL design. A complete design flow from physical simulation to VHDL simulation, delays optimization, layouting and back-annotation is presented. The correctness of the timing models has been verified in an experiment with 4 /spl times/ 15 shift register.

RSFQ digital signal processor for interference cancellation

RSFQ high performance digital signal processor capable to perform up to 13 13-bit fixed-point GMACS has been designed for use in successive interference canceller in W-CDMA wireless systems. The performance of the processor has been verified by numerical simulations and VHDL simulation using accurate modeling of the RSFQ gates. Components of the processor, 4 /spl times/ 4 and 5 /spl times/ 5 parallel multipliers, 4 /spl times/ 5, 20 /spl times/ 5 and 4 /spl times/ 15 parallel shift registers have been designed and experimentally tested.

New Design of an RSFQ Parallel Multiply-Accumulate Unit

The Multiply-Accumulate Unit (MAC) is a central component of a Successive Interference Canceller, an advanced receiver for W-CDMA base stations. A 4*4 twos complement fixed point RSFQ MAC with rounding to 5 bits has been simulated using VHDL and maximum performance is equal to 24 GMACS (giga multiple-accumulates per second). The clock distribution network has been re-designed from a linear ripple to a binary tree network in order to eliminate data dependence of the clock propagation speed and reduce number of Josephson junctions in clock lines. The 4*4 bits MAC has been designed for the HYPRES 4.5 kA/cm^2 process and its components have been experimentally tested at low frequency: the 5 bit combiner, using an exhaustive test pattern, had margins on DC bias voltage of +-18% and the 4*4 parallel multiplier had margins equal to +-2%.

Optimization of superconducting microstrip interconnects for rapid single-flux-quantum circuits

In this paper, issues related to the optimization of superconducting passive interconnects are discussed. Results of the microwave optimization of bends, via connections and crossings of superconducting microstrip lines (SMSLs) are reported. The optimum design of the SMSL cross gives more than 95% of transmission and can be well used in a two-bus cross design with up to 14 signal wires. The results have been confirmed by time-domain simulations and measurements.

Scalable Matrix Multiplication With Hybrid CMOS-RSFQ Digital Signal Processor

We report an RSFQ digital signal processor design based on hybrid RSFQ-CMOS memory suitable for a general matrix-on-matrix multiplication algorithm. The DSP consists of an RSFQ multiply-accumulate unit, memory caches and synchronization block, partitioned into multiple chips, and a large CMOS memory. The parameters of the RSFQ DSP are a 10times10 bits multiplication with rounding to 14 bits, an 18-bit accumulator length and a 3.7 Kb memory cache. The maximum simulated clock frequency is equal to 24 GHz for HYPRES 4.5 kA/cm2 process and optimum communication bandwidth with the CMOS memory is 2 Gbps. The simplified version of the RSFQ DSP consisting of a 4times4 MAC with rounding to 5 bits and 17times6 memory caches has been designed for HYPRES 4.5 kA/cm2 process.

Room Temperature Interface for RSFQ Digital Signal Processor

This paper describes a cryogenic multi-chip module (MCM) probe for testing of a superconducting hybrid digital signal processor (DSP) capable of 24 giga multiply accumulate operations per second. The probe has 39 data channels with 4 GHz bandwidth, a 30 GHz high speed clock input line, and 48 biasing lines. The MCM interface board features 164 spring finger contacts for a 30 times 30 mm2 MCM. The probe has low heatload (0.23 W) and provides good magnetic shielding with residual field equal to 250Phi0 over a 5 times 5 mm2 area. The measured time skew between 20 of the 1200 mm data coaxial lines is about 70 ps. The probe allows synchronous data word transmission at 2 Gbps.