Samuel Intiso

Collapse of thermal activation in moderately damped Josephson junctions

We study switching current statistics in different moderately damped Josephson junctions: a paradoxical collapse of the thermal activation with increasing temperature is reported and explained by interplay of two conflicting consequences of thermal fluctuations, which can both assist in premature escape and help in retrapping back into the stationary state. We analyze the influence of dissipation on the thermal escape by tuning the damping parameter with a gate voltage, magnetic field, temperature and an in-situ capacitor.

Time-delay optimization of RSFQ cells

This paper presents timing models for RSFQ cells, based on conventional finite-state machines description. Models have been integrated, validated and verified in physical simulations and are suitable for VHDL design. A complete design flow from physical simulation to VHDL simulation, delays optimization, layouting and back-annotation is presented. The correctness of the timing models has been verified in an experiment with 4 /spl times/ 15 shift register.

Rapid single-flux-quantum circuits for low noise mK operation

Rapid single-flux-quantum (RSFQ) technology has been proposed as control electronics for superconducting quantum bits because of the material and working temperature compatibility. In this work, we consider practical aspects of RSFQ circuit design for low noise low power operation. At the working temperature of 20 mK and operational frequency of 2 GHz, dissipated power per junction is reduced to 25 pW by using 6 νA critical current junctions available at the Hypres and VTT low Jc fabrication process. To limit phonon temperature to 30 mK, a maximum of 40 junctions can be placed on a 5 mm × 5 mm chip. Electron temperature in resistive shunts of Josephson junctions is minimized by use of cooling fins, giving minimum electron temperatures of about 150 mK for the Hypres process and 70 mK for the VTT process.

Room Temperature Interface for RSFQ Digital Signal Processor

This paper describes a cryogenic multi-chip module (MCM) probe for testing of a superconducting hybrid digital signal processor (DSP) capable of 24 giga multiply accumulate operations per second. The probe has 39 data channels with 4 GHz bandwidth, a 30 GHz high speed clock input line, and 48 biasing lines. The MCM interface board features 164 spring finger contacts for a 30 times 30 mm2 MCM. The probe has low heatload (0.23 W) and provides good magnetic shielding with residual field equal to 250Phi0 over a 5 times 5 mm2 area. The measured time skew between 20 of the 1200 mm data coaxial lines is about 70 ps. The probe allows synchronous data word transmission at 2 Gbps.

A high frequency test bench for rapid single-flux-quantum circuits

We have designed and experimentally verified a test bench for high frequency testing of Rapid Single Flux Quantum (RSFQ) circuits. This test bench uses an external tuneable clock signal that is stable in amplitude, phase and frequency. The high frequency external clock reads out the clock pattern stored in a long shift-register. The clock pattern is consequently shifted out at high speed and splitted to feed both the circuit under test and an additional shift register in the test bench for later verification at low speed. This method can be employed for reliable high speed verification of RSFQ circuit operation, with use of only low speed readout electronics. The test bench consists of 158 Josephson junctions and occupied area is 3300 * 660 (mikro meter)^2. It was experimentally verified up to 33 GHz with +- 21.7 % margins on the global bias supply current.