Henrik Fredriksson

Improvement Potential and Equalization Example for Multidrop DRAM Memory Buses

For PC DRAM memory buses, the number of slots per channel have been decreased as signal frequencies increase. This limits the data capacity per channel. In this paper, we show that the slot reduction is not due to fundamental limits of the channel structure but due to signaling schemes. An equalization scheme is presented which enables higher bit-rates with minimum modification of bus structure and memory circuits. The circuitry added to the host side of the bus has reasonable complexity and features very low latency. Measurements of memory-to-host transmissions over a four-drop-bus at 2.6 Gb/s using a 0.13 mum CMOS test-circuit is presented.

2.6 Gb/s over a four-drop bus using an adaptive 12-tap DFE

For PC DRAM buses, the number of slots per channel has decreased as data rates have increased. This limits the maximum memory capacity per channel. Signal equalization can be used to increase bit-rates for channels with a large number of slots and offer a cost effective method to solve the memory capacity problem. This paper presents a blind adaptive decision feedback equalizer (DFE) that enables high data-rates with a large number of slots per channel. Measurements at 2.6 Gb/s over a four-drop bus are presented.

Mixed-signal DFE for multi-drop, gb/s, memory buses - a feasibility study

A decision feedback equalizer (DFE), well suited for implementation in standard CMOS and capable of recovering data sent over a multi-drop memory bus at several Gb/s per wire, is presented. The structure features low latency and permits easy switching of filter coefficient sets, which enables the bus host to receive data from different slaves. Results from near-hardware simulations of 3 Gb/s per wire transmissions over a four tap standard DDR memory bus are presented.

An Extended Transition Energy Cost Model for Buses in Deep Submicron Technologies

In this paper we present and carefully analyze a transition energy cost model aimed for efficient power estimation of performance critical deep submicron buses. We derive an accurate transition energy cost matrix, scalable to buses of arbitrary bit width, which includes properties that closer capture effects present in high-performance VLSI buses. The proposed energy model is verified against Spectre simulations of an implementable bus, including drivers. The average discrepancy between results from Spectre and the suggested model is limited to 4.5% when fringing effects of edge wires is neglected. The proposed energy model can account for effects that limit potential energy savings from bus transition coding.

3-Gb/s, Single-ended Adaptive Equalization of Bidirectional Data over a Multi-drop Bus

This paper presents a design for single-ended adaptive equalization. The design enables mitigation of inter-symbol interference in communication systems where it is desirable to utilize signal processing resources on only one side of a communication channel. Utilizing the reciprocity principle we show that this idea is suitable for both point-to-point and point-to-multi-point links. Simulation results show that the presented design can mitigate ISI generated by a four drop memory bus at 3 Gb/s.

A 3.4 GB/S Low Latency 1 Bit Input Digital FIR-Filter in 0.13 μM CMOS

This paper presents a low latency, one bit input, high-speed FIR-filter designed for multi-Gb/s mixed signal decision feedback equalizers. The filter utilizes a carry-save FIR tap structure and an efficient dual-edge-flip-flop-multiplexer. The filter has been implemented in a standard 0.13 μm CMOS technology. Simulation results from extracted layout shows correct functionality up to 3.4 G words/s with a latency ≪280 ps.