Peter Caputa

An on-chip delay- and skew-insensitive multicycle communication scheme

A synchronous latency-insensitive design (SLID) method that mitigates unknown on-chip global wire delays and removes the need for controlling global clock skew is presented. An SLID-based 5.4mm-long on-chip global bus, fabricated in a standard 0.18mum CMOS process, supports 3Gb/s/wire and accepts plusmn2 clock cycles of data-clock skew. This paper focuses on data synchronization for large global on-chip signals, which has become a difficult issue in high-frequency processor designs

A 3Gb/s/wire global on-chip bus with near velocity-of-light latency

We successfully show the practical feasibility of a purely electrical global on-chip communication link with near velocity-of-light delay. The implemented high-speed link comprises a 5mm long, fully shielded, repeaterless, on-chip global bus reaching 3Gb/s/wire in a standard 0.18/spl mu/m CMOS process. Transmission-line-style interconnects are achieved by routing signal wires in the thicker top metal M6 layer and utilizing a metal M4 ground return plane to realize near velocity-of-light data transmission. The nominal wire delay is measured to 52.8ps corresponding to 32% of the velocity of light in vacuum. A 22% measured worst-case crosstalk induced delay variation is dominated by inductive coupling.

Low-power, low-latency global interconnect

Global interconnects have been identified as a serious limitation to chip scaling, due to their latency and power consumption. We demonstrate a simple scheme to overcome these limitations, based on the utilization of upper-level metals and reduced voltage swing. The upper-level metal allows velocity of light delay if properly dimensioned and power is optimized by an appropriate choice of voltage swing and receiver amplifier.

High Bandwidth, Low-Latency Global Interconnect

Global interconnects have been identified as a serious limitation to chip scaling, due to their limited bandwidth and large delay. A critical analysis of intrinsic limitations of electrical interconnect indicates that these limitations can be overcome. This basic analysis is presented, together with design constraints. We demonstrate a scheme for this, based on the utilization of upper-level metals as transmission lines. A global communication architecture based on a global mesochronous, local synchronous approach allows very high data-rate per wire and therefore very high bandwidth in buses of limited width. As an example, we demonstrate a 320μm wide bus with a capacity of 160Gb/s in a nearly standard 0.18μm process.

An Extended Transition Energy Cost Model for Buses in Deep Submicron Technologies

In this paper we present and carefully analyze a transition energy cost model aimed for efficient power estimation of performance critical deep submicron buses. We derive an accurate transition energy cost matrix, scalable to buses of arbitrary bit width, which includes properties that closer capture effects present in high-performance VLSI buses. The proposed energy model is verified against Spectre simulations of an implementable bus, including drivers. The average discrepancy between results from Spectre and the suggested model is limited to 4.5% when fringing effects of edge wires is neglected. The proposed energy model can account for effects that limit potential energy savings from bus transition coding.

Capacitive crosstalk effects on on-chip interconnect latencies and data-rates

We investigate how crosstalk affects latency, data-rate, and power dissipation for on-chip global interconnects in a 6-layer 0.18/spl mu/m CMOS process. A simplified analytical interconnect description is compared to circuit simulations of a field solver extracted wire model. We show how repeater insertion can be utilized to achieve wave pipelining, which pushes maximum data-rate beyond the classical limit. Compared to simulations, the analytical model is pessimistic by 10% for latency, 30% for maximum data-rate, and 35% for power dissipation, highlighting the importance of avoiding too simple wire representations.

High-speed on-chip interconnect modeling for circuit simulation

We investigate the relevance of inductance in interconnect models through simulation of an on-chip bus described by a HSPICE W-element, a RLC-network, and a RC-network, respectively. For worst-case delay estimations, we show that the simplest RC-model h sufficient. We further demonstrate the importance of including inductance in noise and edge-rate simulations. For the longest interconnect investigated, the W-element and RC-network differ by 20.6% in overshoot, 156% in ground noise, 53.2% in crosstalk and 61.7% in edge-rule simulations. The W-element and RLC-network never diverge by more than 2% in overshoot, 12.4% in ground noise, 8.9% in crosstalk and 5.6% in edge-rate simulations.

A low-swing single-ended L1 cache bus technique for sub-90nm technologies

This paper describes a 3.3 GHz low-swing single-ended L1 cache bus in 1.2 V, 90 nm dual-Vt CMOS technology. Accurate RLCK-modeling of the interconnect topology has been conducted using a 3D field solver. A signal-swing reduction of 25% and efficient sense amplifier-based receiver are employed to reach 3.3 GHz, 2.24 mW operation at 1.2 V and 110/spl deg/C. 70% energy and 54% peak-current reduction is achieved over an optimized high-performance conventional dynamic cache bus scheme. The design is fully functional up to 6.1 GHz operating-frequency with a 54% eye opening.