Martin Hansson

Jitter Characteristic in Charge Recovery Resonant Clock Distribution

This paper is focused on analysis and suppression of clock jitter in charge recovery resonant clock distribution networks. In the presented analysis, by considering the data-dependent nature of the generated jitter, the reason for the undesired jitter-peaking phenomenon is investigated. The analysis has been verified by measurements on a test chip fabricated in 0.13-mum standard CMOS process. The chip includes a fully integrated 1.5-GHz LC clock resonator with a passive (bufferless) clock distribution network, which directly drives the clocked devices in pipelined data path circuits. Furthermore, a jitter suppression technique based on injection locking is presented. Measurement results show about 50% peak-to-peak clock jitter reduction from 28.4 ps down to 14.5 ps after injection locking.

1.56 GHz On-chip Resonant Clocking in 130nm CMOS

This paper describes a successful experiment of 1.56-GHz on-chip LC-tank resonant clock oscillator, which directly drives 2times896 flip-flops, without intermediate buffers. Detailed power measurements of a test-chip in 130-nm CMOS technology show that the proposed resonant clocking technique results in 57 % lower clock power and 15-30 % lower total chip power compared to the conventional clocking strategy implemented on the same chip. Furthermore, clock jitter measurements show a worst-case peak-to-peak jitter of 28.4 ps (or 14.5 ps using injection locking) across 0-to-80 % data activity in flip-flops and the data-path logic

Comparative Analysis of Process Variation Impact on Flip-Flop Power-Performance

This paper presents an analysis of process variation impact on four flip-flops in 90-nm CMOS. The analyzed flip-flops are compared for required delay overhead and timing uncertainty. The analysis shows that the plusmn2sigma delay variation for two standard master-slave flip-flops is 30% due to random process variation. Pulsed and sense-amplifier based flip-flops suffer 2-2.5times higher delay variation compared to the master-slave flip-flops. Further, the delay variation in the master-slave flip-flops is 2.7times larger than the delay variation in a 5-stage inverter-chain. Therefore, the process variation impact on flip-flops will dominate over the delay spread of the logic.

Jitter Characteristic in Resonant Clock Distribution

This paper presents a detailed clock jitter characteristic analysis of a fully integrated 1.5-GHz resonant clocking fabricated in 130-nm CMOS, with 57% total clock power saving, compared to the conventional clocking implemented in the same test-chip. The jitter measurement result is in good agreement with the jitter analysis. Furthermore, a jitter-suppression technique based on injection locking phenomenon has been utilized to reduce the clock jitter and to solve the jitter peaking problem. Measurements show about 50% peak-to-peak clock jitter reduction from 28.4 ps to 14.5 ps after the activation of the injection locking

Power-performance analysis of sinusoidally clocked flip-flops

This paper can be viewed as a supplement to recent interest in different on-chip resonant clocking techniques. We present a study on the impact of sinusoidal clock signals on power and performance of six conventional flip-flops. The dominating effects are delay penalties of 20-30 % for the best flip-flops, and reduced race-margins. Two-phase master-slave flip-flops and single-phase sense-amplifier flip-flops both obtain robust timing behavior, and minimum power-delay degradation.

A process variation tolerant technique for sub-70nm latches and flip-flops

This paper describes a sub-70nm circuit technique that compensates the impact of the increasingly large process variations on latches and flip-flops. In contrast to the traditional design for worst-case process corners, we utilize a variable keeper circuit that preserves the robustness of storage nodes across the process corners, without degrading the overall chip performance. Power and delay improvements of 7% and 12% respectively have been observed for wide static MUX-latch circuits in a 65nm CMOS technology. Moreover, the proposed technique enables functional flip-flops with weak uninterrupted keepers leading to over 9% clock power reduction.

Low-power bufferless resonant clock distribution networks

The major design challenges toward a highly power- efficient bufferless resonant clock distribution network is discussed. The presented discussion is supported by measurements on three different clock distribution networks implemented in a test chip fabricated in 0.13-mum standard CMOS process. In addition to presenting a detailed power comparison between these networks and the conventional buffer-driven scheme, the clock jitter characteristic in bufferless clock distribution is discussed. Furthermore, injection-locking phenomenon is utilized to suppress data- dependent jitter and to achieve a low-jitter clock distribution.

A low clock load conditional flip-flop

We describe a low clock load conditional transmission-gate flip-flop aimed at reducing on-chip clock power consumption. It utilizes a scalable and simple leakage compensation technique, which injects additional leakage current in opposite direction, thus compensating for the worst-case leakage. During any low frequency operation, the flip-flop is configured as a static flip-flop with increased functional robustness. Post-layout simulations show a 30 % clock power reduction compared to a conventional static flip-flop.

An Extended Transition Energy Cost Model for Buses in Deep Submicron Technologies

In this paper we present and carefully analyze a transition energy cost model aimed for efficient power estimation of performance critical deep submicron buses. We derive an accurate transition energy cost matrix, scalable to buses of arbitrary bit width, which includes properties that closer capture effects present in high-performance VLSI buses. The proposed energy model is verified against Spectre simulations of an implementable bus, including drivers. The average discrepancy between results from Spectre and the suggested model is limited to 4.5% when fringing effects of edge wires is neglected. The proposed energy model can account for effects that limit potential energy savings from bus transition coding.

An Energy-Efficient 32-bit Multiplier Architecture in 90-nm CMOS

This paper describes an energy-efficient 32-bit multiplier based on a modified Booth-encoding scheme in a 90-nm CMOS technology. Further power-performance and area comparisons are presented, between the proposed architecture and a conventional Wallace tree based multiplier. Simulation results shows 47 % better energy-efficiency at the same delay and 24% lower area compared to the conventional multiplier