Henrik Hovsepyan

3D IC TSV‐Based Technology: Stress Assessment For Chip Performance

Potential challenges with managing mechanical stress distributions and the consequent effects on device performance for advanced 3D through‐silicon‐via (TSV) based technologies are outlined. A set of physics‐based compact models of a multi‐scale simulation flow for assessment of the mechanical stress across the device layers in the silicon chips stacked and packaged with the 3D TSV technology is proposed. A calibration technique based on fitting to measured transistor electrical characteristics of a custom designed test‐chip is proposed.

Stress assessment for device performance in three-dimensional IC: linked package-scale/die-scale/feature-scale simulation flow

Abstract. Potential challenges with managing mechanical stress and the consequent effects on device performance for advanced three-dimensional (3-D) IC technologies are outlined. The growing need in a simulation-based design verification flow capable of analyzing a design of 3-D IC stacks and detecting across-die out-of-spec variations in MOSFET electrical characteristics caused by the die thinning and stacking-induced mechanical stress is addressed. The development of a multiscale simulation methodology for managing mechanical stresses during a sequence of designs of 3-D IC dies, stacks, and packages is focused. A set of physics-based compact models for a multiscale simulation is proposed to assess the mechanical stress across the device layers in silicon chips stacked and packaged with the 2.5D interposer-based, and true 3-D through silicon via-based technology. A simulation flow is developed for the hot-spot checking in different types of devices/circuits such as digital, analog, analog matching, memory, IO, characterized by different sensitivities to the stress-induced mobility variations. A calibration technique based on fitting to measured electrical characteristics of the test-chip devices is presented. The limited characterization or measurement capabilities for 3-D IC stacks and a strict “good die” requirement make this type of analysis critical in order to achieve an acceptable level of functional and parametric yield.

Stress-induced Effects Caused by 3D IC TSV Packaging in Advanced Semiconductor Device Performance

Potential challenges with managing mechanical stress and the consequent effects on device performance for advanced 3D through‐silicon‐via (TSV) based technologies are outlined. The paper addresses the growing need in a simulation‐based design verification flow capable to analyze a design of 3D IC stacks and to determine across‐die out‐of‐spec variations in device electrical characteristics caused by the layout and through‐silicon‐via (TSV)/package‐induced mechanical stress. The limited characterization/measurement capabilities for 3D IC stacks and a strict “good die” requirement make this type of analysis critical for the achievement of an acceptable level of functional and parametric yield and reliability. The paper focuses on the development of a design‐for‐manufacturability (DFM) type of methodology for managing mechanical stresses during a sequence of designs of 3D TSV‐based dies, stacks and packages. A set of physics‐based compact models for a multi‐scale simulation to assess the mechanical stress ac...

Control of design specific variation in etch-assisted via pattern transfer by means of full-chip simulation

A novel model-based algorithm provides a capability to control full-chip design specific variation in pattern transfer caused by via/contact etch processes. This physics based algorithm is capable to detect and report etch hotspots based on the fab defined thresholds of acceptable variations in critical dimension (CD) of etched shapes for a prospective dry etch process step. It can be used also as a tool for etch process optimization to capture the impact of a variety of patterns presented in a particular design. A realistic set of process parameters employed by the developed model allows using this novel via-contact etch (VCE) EDA tool for the design aware process optimization in addition to the ¿standard¿ process aware design optimization.