Armen Kteyan

Microstructure Effect on EM-Induced Degradations in Dual Inlaid Copper Interconnects

A novel physical model and a simulation algorithm are used to predict electromigration (EM)-induced stress evolution in dual inlaid copper interconnects. The aim of the current simulation was to investigate the dual effect of the microstructure, which consists of the effect of grain boundaries (GBs) and the effect of texture-related variations of the modulus of elasticity on the stress evolution in copper lines caused by EM. The major difference between our approach and the previously described ones is the accounting of additional stress generated by the plated atoms. The results of the numerical simulation have been proven experimentally by EM degradation studies on fully embedded dual inlaid copper interconnect test structures and by subsequent microstructure analysis, mainly based on electron backscatter diffraction (EBSD) data. The virtual EM-induced void formation, movement, and growth in a copper interconnect were continuously monitored in an in situ scanning electron microscopy experiment. The copper microstructure, particularly the orientation of grains and GBs, was determined with EBSD. For interconnects with interfaces that resist atomic transport and where GBs are the important pathways for atom migration, degradation and failure processes are completely different for microstructures with randomly oriented GBs compared with ldquobamboolikerdquo microstructures. The correspondence between simulation results and experimental data indicates the applicability of the developed model for optimization of the physical and electrical design rules.

Physics-Based Electromigration Models and Full-Chip Assessment for Power Grid Networks

This paper presents a novel approach and techniques for physics-based electromigration (EM) assessment in power delivery networks of very large scale integration systems. An increase in the voltage drop above the threshold level, caused by EM-induced increase in resistances of the individual interconnect branches, is considered as a failure criterion. It replaces a currently employed conservative weakest branch criterion, which does not account an essential redundancy for current propagation existing in the power-ground (P/G) networks. EM-induced increase in the resistance of the individual grid branches is described in the approximation of the recently developed physics-based formalism for void nucleation and growth. An approach to calculation of the void nucleation times in the group of branches comprising the interconnect tree is implemented. As a result, P/G networks become time-varying linear networks. A developed technique for calculating the hydrostatic stress evolution inside a multibranch interconnect tree allows to avoid over optimistic prediction of the time-to-failure made with the Blech-Black analysis of individual branches of interconnect tree. Experimental results obtained on a number of International Business Machines Corporation benchmark circuits show that the proposed method will lead to less conservative estimation of the lifetime than the existing Black-Blech-based methods. It also reveals that the EM-induced failure is more likely to happen at the place where the hydrostatic stress predicted by the initial current density is large and is more likely to happen at longer times when the saturated void volume effect is taken into account.

3D IC TSV‐Based Technology: Stress Assessment For Chip Performance

Potential challenges with managing mechanical stress distributions and the consequent effects on device performance for advanced 3D through‐silicon‐via (TSV) based technologies are outlined. A set of physics‐based compact models of a multi‐scale simulation flow for assessment of the mechanical stress across the device layers in the silicon chips stacked and packaged with the 3D TSV technology is proposed. A calibration technique based on fitting to measured transistor electrical characteristics of a custom designed test‐chip is proposed.

Postvoiding Stress Evolution in Confined Metal Lines

Electromigration (EM)-induced voiding is an important reliability concern in modern integrated circuits. Resistance degradation in interconnect metal lines caused by voiding was studied in this paper theoretically by solving the continuity equation describing the stress evolution caused by growing void. A rigid confinement surrounding a metal line makes inapplicable an approximation of the line edge drift for modeling the void volume evolution unless a line is in a stress-free equilibrium state caused by the presence of a saturated void. Derived analytical solution to the continuity equation with a voidless initial condition provides drastically different stress evolution kinetics in comparison with the case of the line edge drift model. It demonstrates that a large stress gradient, which was developed between the surface of a void precursor (flaw) and a metal, becomes a major driving force for the atom migration from the void surface to the metal. In this case, the initial evolution of the void volume does not depend on the electric current density contrary to the case of the line edge drift approximation characterized by the linear dependence of the void growth rate on the current density. At long time limit, the derived solution provides the same kinetics and the steady state with the stress linearly distributed along the line as in the case of preexisted void. The proposed model results much faster kinetics of the void growth and the line resistance degradation than the line edge drift approximation. Void nucleation time can be employed as a reasonable approximation of the EM-induced time to failure in the confined metal line.

Physics-Based Models for EM and SM Simulation in Three-Dimensional IC Structures

Relaxation of stress generated inside through-silicon via (TSV), in regions of interconnect and regions of silicon adjusted to TSV by microstructure evolution during high-temperature anneal and by wafer/die cooling down to test/operation conditions, is critical for establishing a final equilibrium state. A model for stress relaxation governed by vacancy generation and migration is developed. The comparative study of the steady-state distributions of stress and concentrations of vacancies and plated atoms in via-last and via-middle TSVs allows us to conclude that different types of TSVs are characterized by miniscule differences in the level of generated stress. It is found that the grain size distribution along the TSV height can affect the level of generated stress. TSVs with the largest grains, located in the TSV center, and the smaller ones, located in the TSV top and bottom, seem to generate a smaller outside stress compared to other simulated grain size distributions. It is shown that additional stress gradients in interconnect segments, generated by nearby TSVs, can be relaxed at the proper planed anneal step. The performed simulation analysis allows us to conclude that the introduction of TSVs as a new element in 3-D IC stacking technology does not introduce any significant changes in the EM-related reliability.

Stress assessment for device performance in three-dimensional IC: linked package-scale/die-scale/feature-scale simulation flow

Abstract. Potential challenges with managing mechanical stress and the consequent effects on device performance for advanced three-dimensional (3-D) IC technologies are outlined. The growing need in a simulation-based design verification flow capable of analyzing a design of 3-D IC stacks and detecting across-die out-of-spec variations in MOSFET electrical characteristics caused by the die thinning and stacking-induced mechanical stress is addressed. The development of a multiscale simulation methodology for managing mechanical stresses during a sequence of designs of 3-D IC dies, stacks, and packages is focused. A set of physics-based compact models for a multiscale simulation is proposed to assess the mechanical stress across the device layers in silicon chips stacked and packaged with the 2.5D interposer-based, and true 3-D through silicon via-based technology. A simulation flow is developed for the hot-spot checking in different types of devices/circuits such as digital, analog, analog matching, memory, IO, characterized by different sensitivities to the stress-induced mobility variations. A calibration technique based on fitting to measured electrical characteristics of the test-chip devices is presented. The limited characterization or measurement capabilities for 3-D IC stacks and a strict “good die” requirement make this type of analysis critical in order to achieve an acceptable level of functional and parametric yield.

Microstructure Effect on EM‐induced Degradations in Dual‐Inlaid Copper Interconnects

A novel physical model and a simulation algorithm are used to predict EM induced stress evolution in dual‐inlaid copper interconnects. The aim of the current simulation was to investigate the dual effect of the microstructure, which consists of (a) the effect of GBs as the sources/sinks for vacancies and plated atoms and as the channel for vacancy migration, and (b) the effect of texture‐related variations of the modulus of elasticity on the stress evolution in copper lines caused by EM. The major difference between our approach and the previously described ones is the accounting of additional stress generated by the plated atoms. As it is shown this stress plays an important role in the vacancy equilibration. The results of the numerical simulation have been proven experimentally by EM degradation studies on fully embedded dual‐inlaid copper interconnect test structures and by subsequent microstructure analysis, mainly based on electron backscatter diffraction (EBSD) data. The virtual EM‐induced void for...

Theoretical predictions of EM-induced degradation in test-structures and on-chip power grids with analytical and numerical analysis

Paper discusses the state of the art physics-based analytical modeling and numerical analysis techniques developed for the prediction and description of electromigration (EM) induced conductance degradation of individual interconnect metal lines and on-chip power grids. Mechanical stress evolution caused by an electric current driven redistribution of vacancies and plating atoms, which populate the metal grain boundaries (GB) and interfaces, initiates the growth of preexisted crystal imperfections such as micro cavities and interfacial/inter-granular delaminating. It is described as a major cause of the failure. A role in the failure development played by the interfacial and GB atomic diffusions and their variation is covered. A close relation between the interfacial-adhesion energy and so-called “critical stress” is clarified. A physics-based statistical formulation of EM phenomenon is discussed. Different kind of analytical/numerical techniques employed for analysis of EM degradation in different cases characterized by the scales varying from the size of an individual line to the multibillion segment power grids are discussed. Conditions for employment of 1D EM approximation (Korhonens equation) are validated by direct comparison with results of 3D FEA simulations. Implementation of the novel compact model- and FDA-based approaches for analyzing EM-induced IR-drop degradation in power nets is demonstrated.

Analysis of the Effect of TSV-Induced Stress on Devices Performance by Direct Strain and Electrical Measurements and FEA Simulations

A well-documented effect of the mechanical stresses generated by 3-D IC packaging on the performance of electrical circuits, in some cases leading to their parametric failure, can be controlled by means of stress assessment EDA tools. Verification and calibration of the layout engineered stress models are traditionally performed on the basis of electrical data demonstrating the stress-induced changes in transistors’ drain currents. This paper demonstrates the validity of such an approach in the case of chip-package interaction (CPI)-induced stresses. Through-silicon vias (TSV) were chosen in this paper as a well-controlled stress source. Specially designed test-structures were used for measurements of TSV-induced strains in FET channels by means of the transmission electron microscopy/convergent beam electron diffraction technique. Measured strains were used for calibrating the developed finite-element analysis model of TSV-induced stress. The calibrated stress model was employed for calculating the TSV-induced drain current changes in the nearby devices in the test structures designed for electrical measurements. The demonstrated good fit between the calculated and measured current changes validates the use of electrical measurements for calibrating CPI stress assessment models.

Physics-based simulation of EM and SM in TSV-based 3D IC structures

Evolution of stresses in through-silicon-vias (TSVs) and in the TSV landing pad due to the stress migration (SM) and electromigration (EM) phenomena are considered. It is shown that an initial stress distribution existing in a TSV depends on its architecture and copper fill technology. We demonstrate that in the case of proper copper annealing the SM-induced redistribution of atoms results in uniform distributions of the hydrostatic stress and concentration of vacancies along each segment. In this case, applied EM stressing generates atom migration that is characterized by kinetics depending on the preexisting equilibrium concentration of vacancies. Stress-induced voiding in TSV is considered. EM induced voiding in TSV landing pad is analyzed in details.