Jun-Ho Choy

3D IC TSV‐Based Technology: Stress Assessment For Chip Performance

Potential challenges with managing mechanical stress distributions and the consequent effects on device performance for advanced 3D through‐silicon‐via (TSV) based technologies are outlined. A set of physics‐based compact models of a multi‐scale simulation flow for assessment of the mechanical stress across the device layers in the silicon chips stacked and packaged with the 3D TSV technology is proposed. A calibration technique based on fitting to measured transistor electrical characteristics of a custom designed test‐chip is proposed.

Stress assessment for device performance in three-dimensional IC: linked package-scale/die-scale/feature-scale simulation flow

Abstract. Potential challenges with managing mechanical stress and the consequent effects on device performance for advanced three-dimensional (3-D) IC technologies are outlined. The growing need in a simulation-based design verification flow capable of analyzing a design of 3-D IC stacks and detecting across-die out-of-spec variations in MOSFET electrical characteristics caused by the die thinning and stacking-induced mechanical stress is addressed. The development of a multiscale simulation methodology for managing mechanical stresses during a sequence of designs of 3-D IC dies, stacks, and packages is focused. A set of physics-based compact models for a multiscale simulation is proposed to assess the mechanical stress across the device layers in silicon chips stacked and packaged with the 2.5D interposer-based, and true 3-D through silicon via-based technology. A simulation flow is developed for the hot-spot checking in different types of devices/circuits such as digital, analog, analog matching, memory, IO, characterized by different sensitivities to the stress-induced mobility variations. A calibration technique based on fitting to measured electrical characteristics of the test-chip devices is presented. The limited characterization or measurement capabilities for 3-D IC stacks and a strict “good die” requirement make this type of analysis critical in order to achieve an acceptable level of functional and parametric yield.

Accurate full-chip estimation of power map, current densities and temperature for EM assessment

Full-chip power ground electro-migration assessment requires a power map, thermal map and checks for IR drops exceeding the design specifications. This paper provides a survey of the three main computation operations required to get these information.

Theoretical predictions of EM-induced degradation in test-structures and on-chip power grids with analytical and numerical analysis

Paper discusses the state of the art physics-based analytical modeling and numerical analysis techniques developed for the prediction and description of electromigration (EM) induced conductance degradation of individual interconnect metal lines and on-chip power grids. Mechanical stress evolution caused by an electric current driven redistribution of vacancies and plating atoms, which populate the metal grain boundaries (GB) and interfaces, initiates the growth of preexisted crystal imperfections such as micro cavities and interfacial/inter-granular delaminating. It is described as a major cause of the failure. A role in the failure development played by the interfacial and GB atomic diffusions and their variation is covered. A close relation between the interfacial-adhesion energy and so-called “critical stress” is clarified. A physics-based statistical formulation of EM phenomenon is discussed. Different kind of analytical/numerical techniques employed for analysis of EM degradation in different cases characterized by the scales varying from the size of an individual line to the multibillion segment power grids are discussed. Conditions for employment of 1D EM approximation (Korhonens equation) are validated by direct comparison with results of 3D FEA simulations. Implementation of the novel compact model- and FDA-based approaches for analyzing EM-induced IR-drop degradation in power nets is demonstrated.

Full-chip electromigration assessment: Effect of cross-layout temperature and thermal stress distributions

Many prior works have investigated electromigration (EM) on full-chip power grid interconnects, which has become one of major reliability concerns in nanometer VLSI design. However, most of the published results were obtained under the assumption of uniformly distributed temperature and/or residual stress across interconnects. In this paper, we demonstrate the implementation of novel methodology and flow for full-chip EM assessment on the multi-layered power grid networks of a 32nm test-chip and investigate the impacts of the within-die temperature and thermal stress variations on the failure rate. The proposed approach is based on recently developed physics-based EM models and the EM-induced IR-drop degradation criterion that replaces the traditional conservative weakest segment method. The cross-layout temperature distribution caused by power dissipations in devices and by interconnect Joule heating has been characterized and taken into account in the full-chip EM assessment methodology. Results of the simulations performed on the analyzed multi-layered power/ground nets show that traditional assumption of the uniform average temperature leads to inaccurate predictions of the time-to-failure (TTF). Furthermore, the consideration of thermal stress variation results in a retarded EM induced degradation.

Stress-induced Effects Caused by 3D IC TSV Packaging in Advanced Semiconductor Device Performance

Potential challenges with managing mechanical stress and the consequent effects on device performance for advanced 3D through‐silicon‐via (TSV) based technologies are outlined. The paper addresses the growing need in a simulation‐based design verification flow capable to analyze a design of 3D IC stacks and to determine across‐die out‐of‐spec variations in device electrical characteristics caused by the layout and through‐silicon‐via (TSV)/package‐induced mechanical stress. The limited characterization/measurement capabilities for 3D IC stacks and a strict “good die” requirement make this type of analysis critical for the achievement of an acceptable level of functional and parametric yield and reliability. The paper focuses on the development of a design‐for‐manufacturability (DFM) type of methodology for managing mechanical stresses during a sequence of designs of 3D TSV‐based dies, stacks and packages. A set of physics‐based compact models for a multi‐scale simulation to assess the mechanical stress ac...

Control of design specific variation in etch-assisted via pattern transfer by means of full-chip simulation

A novel model-based algorithm provides a capability to control full-chip design specific variation in pattern transfer caused by via/contact etch processes. This physics based algorithm is capable to detect and report etch hotspots based on the fab defined thresholds of acceptable variations in critical dimension (CD) of etched shapes for a prospective dry etch process step. It can be used also as a tool for etch process optimization to capture the impact of a variety of patterns presented in a particular design. A realistic set of process parameters employed by the developed model allows using this novel via-contact etch (VCE) EDA tool for the design aware process optimization in addition to the ¿standard¿ process aware design optimization.

Design specific variation in via/contact pattern transfer: Full chip analysis

A novel model-based algorithm provides a capability to control full chip design specific variation in pattern transfer caused by via/contact etch processes. This physics-based algorithm is capable of detecting and reporting hot spots based on the fab defined thresholds of acceptable variations in the critical dimension of etched shapes. It can also be used as a tool for etch process optimization to capture the impact of a variety of patterns presented in a particular design. A realistic set of process parameters employed by the developed model allows using this novel via-contact etch electronic design automation tool for the design-aware process optimization in addition to the “standard” process-aware design optimization. Measurements of the postetch geometries of contact holes etched in the organosilicate glass with fluorocarbon plasma (C4F8∕N2∕Ar) are used for model validation and calibration.