Henry Selvaraj

Brain MRI Slices Classification Using Least Squares Support Vector Machine

Abstract This research paper proposes an intelligent classification technique to identify normal and abnormal slices of brain MRI data. The manual interpretation of tumor slices based on visual examination by radiologist/physician may lead to missing diagnosis when a large number of MRIs are analyzed. To avoid the human error, an automated intelligent classification system is proposed which caters the need for classification of image slices after identifying abnormal MRI volume, for tumor identification. In this research work, advanced classification techniques based on Least Squares Support Vector Machines (LS-SVM) are proposed and applied to brain image slices classification using features derived from slices. This classifier using linear as well as nonlinear Radial Basis Function (RBF) kernels are compared with other classifiers like SVM with linear and nonlinear RBF kernels, RBF classifier, Multi Layer Perceptron (MLP) classifier and K-NN classifier. From this analysis, it is observed that the propose...

A General Approach to Boolean Function Decomposition and its Application in FPGABased Synthesis

An effective logic synthesis procedure based on parallel and serial decomposition of a Boolean function is presented in this paper. The decomposition, carried out as the very first step of the .synthesis process, is based on an original representation of the function by a set of r-partitions over the set of minterms. Two different decomposition strategies, namely serial and parallel, are exploited by striking a balance between the two ideas. The presented procedure can be applied to completely or incompletely specified, single- or multiple-output functions and is suitable for different types of FPGAs including XILINX, ACTEL and ALGOTRONIX devices. The results of the benchmark experiments presented in the paper show that, in several cases, our method produces circuits of significantly reduced complexity compared to the solutions reported in the literature.

An application of functional decomposition in ROM-based FSM implementation in FPGA devices

Modern FPLD devices have very complex structure. They combine PLA like structures, as well as FPGA and even memory-based structures. However lack of appropriate synthesis methods do not allow fully exploiting the possibilities the modern FPLDs offer. The paper presents a general method for the synthesis targeted to implementation of sequential circuits using embedded memory blocks. The method is based on the serial decomposition concept and relies on decomposing the memory block into two blocks: a combinational address modifier and a smaller memory block. An appropriately chosen decomposition strategy may allow reducing the required memory size at the cost of additional logic cells for address modifier implementation. This makes possible implementation of FSMs that exceed available memory by using embedded memory blocks and additional programmable logic.

Balanced multilevel decomposition and its applications in FPGA-based synthesis

A general decomposition concept is presented in this paper. The main strategy behind the presented Multilevel Decomposition Method is striking a balance between serial decomposition and parallel decomposition. The method is applicable to a variety of Field Programmable Gate Arrays and allows trading-off area and delay of final implementation. The results prove that the method is efficient and does not suffer from its generality.

Fingerprint verification using wavelet transform

Fingerprint verification is one of the most reliable personal identification methods and it plays a very important role in forensic and civilian applications. However, manual fingerprint verification is so tedious, time-consuming, and expensive in that it is incapable of meeting todays increasing performance requirements. Hence, an automatic fingerprint identification system (AFIS) is widely needed. Wavelet transform which has wide range of applications such as image compression, denoising noisy data, texture classification, etc., is used in this paper, for fingerprint verification. It describes the design and implementation of an offline fingerprint verification system using wavelet transform. In this method, matching can be done between the input image and the stored template without resorting to exhaustive search using the extracted feature. The experimental results show that the wavelet transform based approach is better than the existing minutiae based method and it takes less response time which is more suitable for online verification, with high accuracy.

Efficient Implementation of digital filters with use of advanced synthesis methods targeted FPGA architectures

This paper presents an efficient method for implementation of digital filters targeted FPGA architectures. The traditional approach is based on application of general purpose multipliers. However, performance of multipliers implemented in FPGA architectures does not allow to constructs high performance digital filters. In this paper application of distributed arithmetic is demonstrated. Since in this approach combinational LUT blocks replace general purpose multipliers, it is possible to construct digital filters of very high performance. However LUT blocks can be of considerable size thus advanced synthesis methods have to be used to map them efficiently into FPGA resources. In this paper and application of the functional decomposition based synthesis has been investigated. This method is recognised as the best synthesis method targeted FPGA architectures and allows significant improvements in digital filters implementation. The paper presents many examples confirming that decomposition allows reduction of logic cell utilisation of filter implementation based on distributed arithmetic concept with no performance degradation and even increasing it.

Content based image retrieval using a neuro-fuzzy technique

In this paper, we propose a neuro-fuzzy technique for content based image retrieval. The technique is based on fuzzy interpretation of natural language, neural network learning and searching algorithms. Firstly, fuzzy logic is developed to interpret natural expressions such as mostly, many and few. Secondly, a neural network is designed to learn the meaning of mostly red, many red and few red. The neural network is independent to the database used, which avoids re-training of the neural network. Finally, a binary search algorithm is used to match and display neural networks output and images from database. The proposed technique is very unique and the originality of this research is not only based on hybrid approach to content based image retrieval but also on the new idea of training neural networks on queries. One of the most unique aspects of this research is that neural network is designed to learn queries and not databases. The technique can be used for any real-world online database. The technique has been implemented using CGI scripts and C programming language. Experimental results demonstrate the success of the new approach.

Distributed Processing Applications for UAV/drones: A Survey

Distributed Processing Systems are the ones that include multiple devices (which could be of many types, such as PC computers, mobile devices etc.) that have computational and communication capabilities. Their computational power is jointly used for collaborative processing of variety of tasks – and this processing is realized in distributed manner. UAV - Unmanned Aerial Vehicles (also called drones) gain significant attention over recent years. They have been employed to realize multiple tasks such as surveillance or environmental monitoring. First implementations were based on single UAV, later the potential of multiple UAVs collaborating in a team was noticed. Many applications were implemented in distributed manner, using multiple collaborative UAVs and the distributed processing systems principles. In this paper we survey the applications implemented over cooperative teams of UAVs that operate as distributed processing systems.

Fast and efficient processor allocation algorithm for torus-based chip multiprocessors

Processor Allocator (PA) is a crucial factor in modern Chip MultiProcessors (CMPs). A modern CMP uses Network on Chip (NoC) as communication technique between cores. Thus, the topology of the implemented NoC has also significant impact on the CMPs performance. A good processor allocation technique needs to be fast and ensure the highest possible system utilization. In this paper, we propose a processor allocation technique for such an efficient and fast PA. The PA is driven by a Bit Map Allocation for Torus (BMAT) algorithm, which is a technique designed for k-ary 2-cube topology. The proposed BMAT scheme is presented and described along with a new Busy List Allocation for Torus (BLAT), Sorting Allocation for Torus (SAT) and Stack Based Allocation for Torus (SBAT) algorithms. The presented techniques are compared with previously known important schemes for k-ary 2-mesh topology. The research ideas have been verified using experiments that have also been described in the paper. The presented simulation results reveal that the proposed processor allocation algorithm for k-ary 2-cube, as a technique for PA, achieves better allocation time than all other existing algorithms while the CMP with such a PA is characterized by very high system utilization.

Hardware implementation of processor allocation schemes for mesh-based chip multiprocessors

Well-designed Processor Allocator (PA) is an important factor in modern Chip MultiProcessors (CMPs). It needs to be fast as well as area and energy efficient, because it is only a small component of the CMP. In this paper, we propose an architecture for such an efficient and fast PA. The PA structure is based on bit map approach and is driven by an Improved First Fit (IFF) algorithm, which is presented and described. Together with the proposed IFF technique, a new Improved Adaptive Scan (IAS) and an Improved Quick Allocation (IQA) algorithms are introduced and discussed and compared with previously known important techniques. The presented synthesis results reveal that the proposed PA achieves good frequency results while, at the same time is characterized by low logic utilization.