Nikolaus Kerö

Embedded SynUTC and IEEE 1588 clock synchronization for industrial Ethernet

This article describes the architecture and implementation of two systems on a chip, which support high accuracy clock synchronization over Ethernet networks. The synchronization is based on the SynUTC technology and on the novel IEEE 1588 standard for a precision clock synchronization protocol for networked measurement and control systems. The network interface node on one hand provides all necessary hardware support to be flexibly used in a broad range of applications. The switch add-on on the other hand accounts for the packet delay uncertainties of Ethernet switches and is crucial for high accuracy clock synchronization.

A Network Time Interface M-Module for Distributing GPS-Timeover LANs

This paper provides a comprehensive overview of our Network Time Interface (NTI) M-Module, which facilitates high-accuracy time distribution in LAN-based distributed real-time systems. Built around our custom UTCSU VLSI chip, it hosts all the hardware support required for interval-based external clock synchronization: A high-resolution state- and rate-adjustable clock, local accuracy intervals, interfaces to GPS receivers, and various timestamping features. Maximum network controller and CPU independence ensures that the available NTI prototype can be employed in virtually any COTS-based system with MA-Module interface. Our experimental evaluation shows that time distribution with μs-accuracy is possible even in Ethernet-based system architectures, provided that the available configuration parameters are suitably chosen to cope with the various hidden sources of timing uncertainty.

Towards high accuracy in IEEE 802.11 based clock synchronization using PTP

The introduction of the precision time protocol has brought forth the possibility to have a standardised synchronization mechanism in networks, independent from the actual communication technology. However, it can be observed, for example in the annexes of the standard, that many implementations focus only on Ethernet based communication. The logical next step is to investigate how this protocol will fare when used for synchronizing clocks in a distributed manner over IEEE 802.11 based devices. The availability of features like roaming, the broadcast nature of the wireless medium and different hardware platform architectures require an investigation on how clock synchronization can be realized in wireless environments. This paper proposes an approach to import the precision time protocol to IEEE 802.11. Furthermore, standard nodes are enhanced with software timestamping, leading to a synchronization accuracy of a few microseconds.

Master failures in the Precision Time Protocol

If all clocks within a distributed system share the same notion of time, the application domain can gain several advantages. Among those is the possibility to implement real-time behavior, accurate time stamping, and event detection. However, with the wide spread application of clock synchronization another topic has to be taken into consideration: the fault tolerance. The well known clock synchronization protocol IEEE1588 (precision time protocol, PTP), is based on a master/slave principle, which has one severe disadvantage. This disadvantage is the fact that the failure of a master automatically requires the re-election of a new master. The start of a master election based on timeout and thus takes a certain time span during which the clocks are not synchronized and thus running freely. Moreover the usage of a new master also requires new delay measurements, which prolong the time of uncertainty as well. This paper analyzes the results of such a master failure and proposes democratic master groups instead of hot-stand-by masters to overcome this problem by. It is shown by means of simulation that the proposed solution will not deteriorate the accuracy of the slave clocks in case of a master failure.

Compensation of asymmetrical latency for ethernet clock synchronization

Clock synchronization has become an indispensable service in most distributed systems as it allows to sort events on a common time scale and coordinate collaborative actions.With the demand for even higher synchronization accuracy, new challenges and barriers have to be tackled to fulfill these requirements. One of them, the inevitable signal propagation time between the devices, is compensated in many state-of-the-art synchronization protocols by round-trip measurements, neglecting any form of delay asymmetry of the communication link. In this paper, we analyze the impact of asymmetry in networks based on the physical layer of copper-based Ethernet and compare different approaches on how to mitigate the impact of asymmetry. We propose a non-invasive system performing asymmetry measurements on a link basis and show that such a system can integrate into existing synchronization solutions.

System integration of an IEEE 802.11 based TDoA localization system

Network entities with synchronized clocks are an enabler for many interesting and innovative applications. Localization of mobile WLAN devices by means of propagation delay measurements and position calculation according to time difference of arrival (TDoA) method is one of the most interesting applications. Those localization techniques are favored over standard signal strength based methods when high accuracy positioning is desired. This paper presents a system that utilizes special synchronized receivers in conjunction with a central unit to locate WLAN devices. The system architecture is described in terms of the integration of all participating entities for both, hardware and software. 1

Digital implementation of the preloaded filter pulse processor

Adapting its processing time to the respective pulse intervals, the Preloaded Filter (PLF_ pulse processor offers optimum resolution together with highest possible throughput rates. The PLF algorithm could be formulated in a recursive manner which made possible its implementation by means of a large field-programmable gate array, as a fast, pipe-lined digital processor with 10 MHz maximum throughput rate. While pre-filter digitization by an ADC with 12 bit resolution and 10 MHz sampling rate resulted in a poorer resolution than that of an analog filter, a digital PLF based on an ADC with 14 bit resolution and 10 MHz sampling rate, surpassed high-quality analog filters in resolution, throughput rate and long-term stability.

A smart capacitive angle sensor

This paper presents a smart capacitive angle sensor suited for automotive and industrial use. To comply with tough constraints of such applications in terms of environmental conditions, unit costs, and physical size, a fully integrated solution is mandatory. However, the limitations and capabilities of a single mixed-signal integrated circuit have considerable impact not only on the hardware architecture of the digital and analog system components, but also on the feasible measurement algorithm. A thorough investigation of all major nonlinear effects leads to an accurate system-level model of the sensor which is used to design a robust and reliable fully integrated sensor system capable of handling signal offset and amplitude variations. In addition, the proposed system recognizes and reacts on electromagnetic disturbances. Measurements taken from a final prototype comply with the simulation results.

Location-based handover in cellular IEEE 802.11 networks for Factory Automation

The use of wireless technologies in Factory Automation is attractive due to several advantages (mobility, cost, etc.); however, to satisfy the requirements of industrial applications, they have to be improved in terms of real-time performance. Handover is a particular weakness in cellular wireless systems, e. g., in IEEE 802.11, since it may introduce delay beyond acceptable bounds. The project “flexWARE - Flexible Wireless Automation in Real-Time Environments” aims at implementing such an infrastructure based on IEEE 802.11. To enhance overall system performance, it offers a localisation service. In this paper we present the flexWARE handover mechanism which exploits localisation to reduce the discovery phase. A performance evaluation, based on simulation and empirical measurements, shows that the mechanism results in a seamless handover for a class of industrial applications.

A novel, high resolution oscillator model for DES systems

High accurate synchronization of clocks in environments with a high number of nodes can take advantage of modern communication networks. However, with the large number of nodes another problem arises: systems of this size cannot any more be evaluated on experimental basis. Therefore, simulation tools and models are required. These simulator models have special requirements which are outlined in this paper. Moreover, a modeling strategy is proposed and demonstrated, which can be implemented for Discrete Event Simulation tools.