Rabab Ezz-Eldin

Traffic-Based Virtual Channel Activation for Low-Power NoC

A large amount of leakage power could be saved by increasing the number of idle virtual channels (VCs) in a network-on-chip (NoC). Low-leakage power switch is proposed to allow saving in power dissipation of the NoC. The proposed NoC switch employs power supply gating to reduce the power dissipation. Two power reduction techniques are exploited to design the proposed switch. Adaptive virtual channel technique is proposed as an efficient technique to reduce the active area using hierarchical multiplexing tree. Moreover, power gating (PG) reduces the average leakage power consumption of proposed switch. The proposed techniques save up to 97% of the switch leakage power. In addition, the dynamic power is reduced by 40%. The traffic-based virtual channel activation (TVA) algorithm is used to determine the traffic status and send adaptation signals to PG units to activate/deactivate the VCs. The TVA algorithm optimally utilizes VCs by deactivating idle VCs to guarantee high-leakage power saving with high throughput. TVA is an efficient and flexible algorithm that defines a set of parameters to be used to achieve minimum degradation in NoC throughput with maximum reduction in leakage power. The whole network average leakage power has been reduced by up to 80% for 2-D-mesh NoC with throughput degradation within only 1%. For 2-D-torus NoC, a saving in power of up to 84% is achieved with <;2% degradation in throughput. The implementation overhead of TVA is negligible.

Low leakage power NoC switch using AVC

Low leakage power switch is proposed to allow saving in power dissipation of the Network on Chip (NoC). The proposed NoC switch employs power supply gating to reduce the power dissipation. Two power reduction techniques are exploited to design the proposed switch. Adaptive Virtual Channel (AVC) technique is proposed as an efficient technique to reduce the active area using hierarchical multiplexing tree. Moreover, power gating reduces the average leakage power consumption of proposed switch. The proposed techniques reduce the leakage power of the switch by up to 97%. In addition, the dynamic power is reduced by up to 54%.

High Throughput Asynchronous NoC Design under High Process Variation

Asynchronous switching is proposed as a robust design to mitigate the impact of process variation in Network on Chip (NoC). Circuit analysis is used to evaluate the influence of process variation on both synchronous and asynchronous designs. The impact of process variation is evaluated on different NoC topologies. Network on chip interconnects and clock distribution network are considered under process variation with the advance in technology. The variation in logic and interconnect are included to evaluate the delay, throughput and leakage power variation with different NoC topologies. In addition, the delay and throughput variation are evaluated for clock distribution network. For asynchronous NoC design, the throughput negligibly decreases under high process variation conditions in different NoC topologies. The throughput variation for synchronous design in all topologies rapidly decreases by up to 25% at the same variation conditions. Synchronous and asynchronous designes are provided for NoC.The throughput of synchronous design rapidly reduces as compared to nominal values for different technologies.The throughput of asynchronous designe under process variation almost remains the same as compared to nominal values for different topologies

Asynchronous high throughput NoC under high process variation

Asynchronous NoC switch is proposed as a robust design to mitigate the impact of process variation. Asynchronous and synchronous network on chip design are implemented to evaluate the impact of process variation on the network throughput. Network on chip interconnects and clock distribution network are considered under process variation with the advance in technology. The variation in logic and interconnect are included to evaluate the delay and throughput variation with different technologies. The throughput negligibly decreases under high process variation conditions in asynchronous NoC switch, while rapidly decreases by up to 25% in synchronous design at the same variation conditions.

High throughput asynchronous NoC switch for high process variation

Asynchronous NoC switch is proposed as a robust design to mitigate the impact of process variation. Circuit analysis is used to evaluate the influence of process variation on both synchronous and asynchronous designs. The delay and throughput variation are evaluated with different technologies. Although the asynchronous switch has large delay variation as compared to synchronous switch, high throughput is achieved under high process variation conditions. The throughput remains unchanged under high process variation conditions in asynchronous NoC switch, while the throughput of synchronous switch is rapidly reduced at the same conditions.

Process Variation Delay and Congestion Aware Routing Algorithm for Asynchronous NoC Design

The effect of process variation (PV) on delay is a major reason to deteriorate the performance in advanced technologies. The performance of different routing algorithms is determined with/without PV for various traffic patterns. The saturation throughput and average message delay are used as performance metrics to evaluate the throughput. PV decreases the saturation throughput and increases the average message delay. PV increases the average message delay by up to 90% and decreases the saturation throughput by up to 29% compared with nominal characteristics of different routing algorithms. Adaptive routing algorithm should be manipulated with the PV. A novel PV delay and congestion aware routing (PDCR) algorithm is proposed for asynchronous network-on-chip design. PDCR is adaptive, low cost, and scalable. The novel routing algorithm outperforms different adaptive routing algorithms in the average delay and saturation throughput for various traffic patterns. PDCR can achieve up to 12%-32% average message delay lower than that of other routing algorithms. Moreover, the proposed scheme yields improvements in saturation throughput by up to 11%-82% compared with other adaptive routing algorithms.

Novel Adaptive Virtual Channels technique for NoC switch

Adaptive Virtual Channel (AVC) is proposed as an efficient novel technique to reduce power dissipation of NoC switch. The proposed NoC switch employs power supply gating to reduce the power dissipation without degrading network performance. Hierarchical multiplexing tree is used to achieve efficient AVC. AVC uses hierarchical multiplexing tree and power gating mechanism to reduce both dynamic and leakage power dissipation of the switch. AVC technique is proposed to reduce the active area using hierarchical multiplexing tree. The dynamic power reduces by 60%. Using the leakage power reduction technique, the average leakage power consumption of Adaptive Virtual Channels is reduced by up to 97%.

Analysis and design of Network on Chip under high process variation

Asynchronous router is proposed as a vigorous design to alleviate the impact of process variation in Network on Chip (NoC). The impact of process variation on the network throughput is evaluated by implementing asynchronous and synchronous network on chip designs. Many Network on Chip topologies are used to evaluate the influence of process variation. Circuit analysis is used to evaluate the impact of process variation on both synchronous and asynchronous designs. The delay, throughput and leakage power variation for different NoC topologies are evaluated with taking into consideration NoC interconnects and clock distribution network under process variation with advanced technology. In advanced technologies, process variation crumbles the performance of routing algorithms. For different traffic patterns, the performance of many routing algorithms is determined. Adaptive routing algorithm should be aware of the process variation. To avert the influence of process variation and congestion for asynchronous NoC design, a novel routing algorithm is presented. Process variation Delay and Congestion aware Routing (PDCR) is proposed as adaptive, low cost and scalable routing algorithm. The performance of different routing algorithms is determined and compared to PDCR with process variation under various traffic patterns. Saturation throughput and average message delay are used to evaluate the different routing algorithms. PDCR achieves high performance as compared to different adaptive routing algorithms under various traffic patterns.

Novel Routing Algorithm for Minimum on Delay with Process Variation and Congestion in Asynchronous NoC

A novel routing algorithm is presented to avoid the impact of process variation and congestion for asynchronous NoC design. Process variation Delay and Congestion aware Routing (PDCR) is proposed as adaptive, low cost and scalable routing algorithm. The performance of PDCR with process variation is determined as compared with different routing algorithms under various traffic patterns. The saturation throughput and average message delay are used as performance metrics. PDCR outperforms different adaptive routing algorithms using various traffic patterns. PDCR can achieve up to 12% - 32% average message delay lower than that of other routing algorithms. Moreover, the proposed scheme yields improvements in saturation throughput by up to 11% - 82% compared with other adaptive routing algorithms.

Low-Power NoC Using Optimum Adaptation

Two power-reduction techniques are exploited to design a low leakage power NoC switch. First, the adaptive virtual channel (AVC) technique is presented as an efficient way to reduce the active area using a hierarchical multiplexing tree of VC groups. Second, power gating reduces the average leakage power consumption of the switch by controlling the supply power of the VC groups. The traffic-based virtual channel activation (TVA) algorithm is presented to determine traffic load status at the NoC switch ports. The TVA algorithm optimally utilizes virtual channels by deactivating idle VC groups to guarantee high leakage power saving without affecting the NoC throughput.