Hideaki Aochi

Bit Cost Scalable Technology with Punch and Plug Process for Ultra High Density Flash Memory

We propose Bit-Cost Scalable (BiCS) technology which realizes a multi-stacked memory array with a few constant critical lithography steps regardless of number of stacked layer to keep a continuous reduction of bit cost. In this technology, whole stack of electrode plate is punched through and plugged by another electrode material. SONOS type flash technology is successfully applied to achieve BiCS flash memory. Its cell array concept, fabrication process and characteristics of key features are presented.

Optimal device structure for Pipe-shaped BiCS Flash memory for ultra high density storage device with excellent performance and reliability

An asymmetric source/drain profile for select gate and metal salicided control gate are successfully realized on Pipe-shaped Bit Cost Scalable (P-BiCS) Flash memory to achieve data storage device with excellent performance and reliability.

Fin-Array-FET on bulk silicon for sub-100 nm trench capacitor DRAM

Fin gate array transistor (Fin-Array-FET) fabricated on bulk silicon substrate is applied to the DRAM cell with the deep trench (DT) capacitor. Fin-Array-FET is designed for the 130 nm technology node and beyond by using the 3-D device simulator (HyDeLEOS) and process simulator (HySyProS). It is demonstrated that the on-current of Fin-Array-FET is 62 /spl mu/A/cell that is about 1.7 times as much as conventional planer array FET, keeping the off-current 0.1 fA/cell. It is also demonstrated that Fin-Array-FET on bulk silicon substrate can relieve of the retention degradation because the channel boron doping can be reduced to more than one order compared to the conventional planar array FET.

BiCS Flash as a Future 3D Non-Volatile Memory Technology for Ultra High Density Storage Devices

In this presentation, recent reports on three dimensional non-volatile memories are reviewed and their pros and cons are discussed. BiCS (Bit Cost Scalable) flash technology is focused as one of the most promising candidates for the future ultra high density storage devices.

Vertex channel array transistor (VCAT) featuring sub-60nm high performance and highly manufacturable trench capacitor DRAM

Novel vertex channel array transistor (VCAT) fabricated on bulk silicon substrate is applied to trench capacitor DRAM cell for the first time. VCAT utilizes the vertexes as channel between top surface and (111) facet of selective epitaxial Si on active areas. It can be fabricated with much simpler process than FIN array transistor reported previously and fit to the process integration of trench capacitor DRAM cell. Almost 2 times higher on-current, smaller sub-threshold swing and less body effect than a conventional planar array transistor are demonstrated.

Vertex Channel Field Effect Transistor (VC-FET) Technology Featuring High Performance and Highly Manufacturable Trench Capacitor DRAM

Vertex channel (VC) transistor is applied to both support devices and array transistor of trench capacitor DRAM for the first time. On-current of VC-FETs is much higher than that of conventional planar devices with keeping sufficiently small off-current. They achieve 15% or much smaller propagation delay (Tpd) of fan-out 3 than planar devices. Furthermore, 1.6 times of on-current as a planar array transistor is achieved by the combination of VCAT and P+poly gate without degradation of retention characteristics

Trench-trench leakage current characteristics in the stacked trench capacitor (STT) cell

Intercell leakage current characteristics of a stacked trench capacitor cell (STT) are investigated. The primary obstacle in downscaling the trench capacitor is the intercell leakage current caused by the parasitic field MOS transistor. This leakage current, called surface leakage current, is significantly reduced in the STT. This reduction results from the STT structure itself. In the STT, the sidewall of the field oxide between neighboring trenches is covered by the storage node electrode. Therefore, most of the electric field lines, originating at the plate electrode, terminate on the storage node electrode. The influence of the plate bias on the Si surface potential beneath the field oxide is weakened by the storage node electrode. The STT has superior trench-trench isolation characteristics, and it is a promising structure for the 16-Mb DRAM and beyond. >

Session 33: Memory technology - DRAM and NOR

This session presents recent advances in 1T DRAM, standard DRAM and NOR flash memory. The 1st Paper by Ki-Whan Song et al., from Samsung demonstrates aggressively scaled 55 nm capacitor-less 1T DRAM cell transistor with non-overlap source and drain. The next paper by T. Ohsawa et al., from Toshiba Corporation proposes autonomous refresh of floating body cell for 1Gb 32nm FBRAM. Hyun Jun Bae at al., from Samsung explore the evaluation of 1T RAM using various operation methods with SOONO device and show the longest retention time ever reported for 1T RAM. T. Schloesser et al., from Qimonda present a 46nm 6F2 buried word line DRAM enabling the smallest cell size of 0.013μm2 published to date. The invited paper by S.Q. Gu et al., from Qualcomm reviews stackable memory of 3D chip integration for mobile application which provides unique opportunity for high BW and low power. The next paper by Wen-Jer Tsai et al., from Macronix reports on highly punchthrough-immune operation for ultra-short-channel hot-carrier injection type non-volatile memory. Finally, C. Gerardi et al., from STMicroelectronics and CEA-LETI demonstrate excellent performance and reliability of Si nano-crystal 4Mb NOR flash in 90nm.