Yoshiaki Fukuzumi

Bit Cost Scalable Technology with Punch and Plug Process for Ultra High Density Flash Memory

We propose Bit-Cost Scalable (BiCS) technology which realizes a multi-stacked memory array with a few constant critical lithography steps regardless of number of stacked layer to keep a continuous reduction of bit cost. In this technology, whole stack of electrode plate is punched through and plugged by another electrode material. SONOS type flash technology is successfully applied to achieve BiCS flash memory. Its cell array concept, fabrication process and characteristics of key features are presented.

Optimal device structure for Pipe-shaped BiCS Flash memory for ultra high density storage device with excellent performance and reliability

An asymmetric source/drain profile for select gate and metal salicided control gate are successfully realized on Pipe-shaped Bit Cost Scalable (P-BiCS) Flash memory to achieve data storage device with excellent performance and reliability.

Improvement of robustness against write disturbance by novel cell design for high density MRAM

A new bit cell designed to have an excellent astroid is presented from the viewpoints of both theory and experiment. The switching mechanism is unique. The robustness against the disturbance of half-selected bits is improved. Its excellent astroid improves thermal stability and has the potential to achieve extremely high density magnetoresistive random access memory (MRAM).

Bit yield improvement by precise control of stray fields from SAF pinned layers for high-density MRAMs

A write-operating window with a 100% functional bit yield was successfully obtained by the control of stray fields from synthetic antiferromagnetic (SAF) pinned layers in conventional magnetic random access memories with rectangular magnetic tunneling junction bits. The stray fields were controlled by a newly developed ion-beam etching technique without causing damage and by a precise setting of the SAF pinned layer thickness, and are balanced with Neel coupling fields. As a result, it was found that symmetric switching astroid curves with no offset were obtained and switching distributions were minimized at the zero offset field.

Design and process integration for high-density, high-speed, and low-power 6F/sup 2/ cross point MRAM cell

A cross point (CP) cell with hierarchical bit line architecture was proposed for magnetoresistive random access memory (MRAM) based in Y. Shimizu et al. (2004). The new CP cell has a potential high density of 6F/sup 2/ and a faster access time than the conventional CP cell. A cell layout design to realize 6F is proposed and associated issues are resolved. Further, a 1Mb MRAM chip based on this structure has been fabricated utilizing 0.13 /spl mu/m CMOS technology and 0.24/spl times/0.48 /spl mu/m/sup 2/ magnetic tunnel junction (MTJ) sandwiched with the most efficient yoke wires ever reported. The access time of 250 ns and 1.5 V operations are successfully demonstrated with the integrated 1Mb chip.

Liner-supported cylinder (LSC) technology to realize Ru/Ta/sub 2/O/sub 5//Ru capacitor for future DRAMs

The concept of liner-supported cylinder (LSC) technology to realize robust formation of cylindrical electrodes with Ru, which has advantages to bring out the best of Ta/sub 2/O/sub 5/ performance, is described. With experimental results including DRAM functionality, we show that LSC-Ta/sub 2/O/sub 5/ capacitor is a promising candidate to realize 0.10 /spl mu/m DRAMs and beyond.

Reduction of Bipolar Disturb of Floating-Body Cell (FBC) by Silicide and Thin Silicon Film Formed at Source and Drain Regions

The cell-to-cell leakage caused by bipolar disturb of the floating-body cell (FBC) has been investigated. In the case of FBC without silicide at the source and drain regions, the change of data “0” to data “1” has been observed in the writing operation to the adjacent cell. However, this leakage can be reduced when the silicide is formed on the thin silicon film at the source and drain regions. It has been clarified that the diffusion of holes inside the n+ region is restricted by the capture of holes at the silicide/silicon interface when silicon thickness reduces. Based on these experimental results, 6F2 layout of FBC can be realized with the conventional logic device process platform.