Masaru Kito

Bit Cost Scalable Technology with Punch and Plug Process for Ultra High Density Flash Memory

We propose Bit-Cost Scalable (BiCS) technology which realizes a multi-stacked memory array with a few constant critical lithography steps regardless of number of stacked layer to keep a continuous reduction of bit cost. In this technology, whole stack of electrode plate is punched through and plugged by another electrode material. SONOS type flash technology is successfully applied to achieve BiCS flash memory. Its cell array concept, fabrication process and characteristics of key features are presented.

Optimal device structure for Pipe-shaped BiCS Flash memory for ultra high density storage device with excellent performance and reliability

An asymmetric source/drain profile for select gate and metal salicided control gate are successfully realized on Pipe-shaped Bit Cost Scalable (P-BiCS) Flash memory to achieve data storage device with excellent performance and reliability.

Trench transformation technology using hydrogen annealing for realizing highly reliable device structure with thin dielectric films

The shape and the surface morphology of the trench structure was successfully transformed by the annealing in hydrogen ambient. The corner was rounded and the surface morphology was smoothened on the inside of the trench. Electrical characteristics of the thin oxide grown in the deep trench capacitor were drastically improved. The hydrogen annealing condition was optimized based on the transformation mechanism.

Fin-Array-FET on bulk silicon for sub-100 nm trench capacitor DRAM

Fin gate array transistor (Fin-Array-FET) fabricated on bulk silicon substrate is applied to the DRAM cell with the deep trench (DT) capacitor. Fin-Array-FET is designed for the 130 nm technology node and beyond by using the 3-D device simulator (HyDeLEOS) and process simulator (HySyProS). It is demonstrated that the on-current of Fin-Array-FET is 62 /spl mu/A/cell that is about 1.7 times as much as conventional planer array FET, keeping the off-current 0.1 fA/cell. It is also demonstrated that Fin-Array-FET on bulk silicon substrate can relieve of the retention degradation because the channel boron doping can be reduced to more than one order compared to the conventional planar array FET.

Vertex channel array transistor (VCAT) featuring sub-60nm high performance and highly manufacturable trench capacitor DRAM

Novel vertex channel array transistor (VCAT) fabricated on bulk silicon substrate is applied to trench capacitor DRAM cell for the first time. VCAT utilizes the vertexes as channel between top surface and (111) facet of selective epitaxial Si on active areas. It can be fabricated with much simpler process than FIN array transistor reported previously and fit to the process integration of trench capacitor DRAM cell. Almost 2 times higher on-current, smaller sub-threshold swing and less body effect than a conventional planar array transistor are demonstrated.

Embedded trench DRAMs for sub-0.10-/spl mu/m generation by using hemispherical-grain technique and LOCOS collar process

For the future system on chip era, the embedded DRAM is one of the most important devices. Since the kinds of device increase and each device must be produced from only 10000 wafers, it is difficult to withdraw the investment cost to fabricate each device. To suppress the investment cost, the devices must be shrunk by changing the integration and the materials as little as possible. In this paper, we propose the trench capacitor scaling strategy. We show that the strategy achieves 30 fF/cell for the 0.08 /spl mu/m trench and reduces the cost of ownership (COO) and raw process time (RPT) of the 0.08 /spl mu/m trench to 80% of 0.18-/spl mu/m trench, with an investment of only

Vertex Channel Field Effect Transistor (VC-FET) Technology Featuring High Performance and Highly Manufacturable Trench Capacitor DRAM

1.6 M. It is achieved by the LOCOS collar process and HSG technique.

Non-volatile semiconductor storage device and method of manufacturing the same

Vertex channel (VC) transistor is applied to both support devices and array transistor of trench capacitor DRAM for the first time. On-current of VC-FETs is much higher than that of conventional planar devices with keeping sufficiently small off-current. They achieve 15% or much smaller propagation delay (Tpd) of fan-out 3 than planar devices. Furthermore, 1.6 times of on-current as a planar array transistor is achieved by the combination of VCAT and P+poly gate without degradation of retention characteristics