Hideaki Konishi

BIST-aided scan test - a new method for test cost reduction

It is common to use ATPG of scan-based design for high fault coverage in LSI testing. However, significant increase in test cost is caused in accordance with increasing design complexity. Recent strategies for test cost reduction combine ATPG and BIST techniques. Unfortunately, these strategies have serious constraints. We propose a new method that employs ATE and BIST structures to apply coded test patterns to LSI circuits. Results obtained using practical circuits show drastic test cost reduction capability of the proposed method.

A method of static compaction of test stimuli

Large numbers of test stimuli impact on test application time and cost of test application. Hence there is the need to keep numbers of test stimuli low while maintaining as high fault coverage as possible. In this paper, static compaction of test stimuli is seen as a minimization problem. The task of static compaction of a set of test stimuli has been formulated as a minimum covering problem. Based on the concept of minimization, a method of static compaction has been developed. Results of experiments conducted to evaluate the method are also presented. The method achieved a significant compaction of sets of test stimuli that had previously been compacted by means of a test generation algorithm that features dynamic compaction.

Test Data Compression of 100x for Scan-Based BIST

The authors have developed a scheme for scan-based BIST that can compress test stimuli and responses by more than 100 times. The scheme is based on a scan-BIST architecture, and combines four techniques: the invert-and-shift operation, run-length compression, scan address partitioning, and LFSR pre-shifting. The scheme achieved a 100times compression rate in environments where Xs do not occur without reducing the fault coverage of the original ATPG vectors. Furthermore, the masking logic was enhanced to reduce data for X-masking so that test data is still compressed to 1/100 in a practical environment where Xs occur. The scheme was applied to five real VLSI chips, and the technique compressed the test data by 100times for scan-based BIST

Test Data Compression for Scan-Based BIST Aiming at 100x Compression Rate

We developed test data compression scheme for scan-based BIST, aiming to compress test stimuli and responses by more than 100 times. As scan-BIST architecture, we adopt BIST-Aided Scan Test (BAST), and combines four techniques: the invert-and-shift operation, run-length compression, scan address partitioning, and LFSR pre-shifting. Our scheme achieved a 100x compression rate in environments where Xs do not occur without reducing the fault coverage of the original ATPG vectors. Furthermore, we enhanced the masking logic to reduce data for X-masking so that test data is still compressed to 1/100 in a practical environment where Xs occur. We applied our scheme to five real VLSI chips, and the technique compressed the test data by 100x for scan-based BIST.

The Application of BIST-Aided Scan Test for Real Chips

It is common to use ATPG of scan-based design for high fault coverage in LSI testing. However, significant increase in test cost is caused in accordance with increasing design complexity. We proposed a new method, BIST-aided scan test (BAST), to reduce test cost in 2OO3 (Hiraide). Since then, we applied this method for about 200 chips, and the result is very successful to reduce test cost with less design flow impact