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Dive into the research topics where Hidehiko Kira is active.

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Featured researches published by Hidehiko Kira.


international microwave symposium | 2003

A 100-GHz distributed amplifier in chip-size package

Satoshi Masuda; Kazuhiko Kobayashi; Hidehiko Kira; Masayuki Kitajima; Masakazu Takesue; Yoshihisa Kamiya; Kazukiyo Joshin

We developed a new millimeter-wave plastic chip size package (CSP) to operate up to 100 GHz by using a thin-film substrate. It has a flip-chip distributed amplifier with inverted microstrip lines that has a bandwidth of beyond 110 GHz. The CSP amplifier achieved a gain of 7.8 dB and a 3 dB bandwidth of 97 GHz, and operated up to 100 GHz as an amplifier. To our knowledge, this value is the highest operating frequency reported to date for a distributed amplifier sealed in a plastic CSP.


cpmt symposium japan | 2016

Development of a stacking technology for large-sized chips using non-conductive film

Hidehiko Kira; Norio Kainuma; Naoaki Nakamura; Takashi Kubota; Takumi Masuyama; Sanae Iijima

A chip stacking process technology using high mass productivity non-conductive film (NCF) has been developed, with assumptions for the central processing unit (CPU) in high-end servers. With this process, a 23 mm by 23 mm chip with a bump pitch of 40 μm was successfully stacked onto another, and 296,000 bumps were jointed in total. In the development of the chip stacking process, in order to measure NCF behavior in the thermo compression flip chip (TCFC) bonding process, the head position detecting mechanism of a flip chip bonder (FCB) measured NCF deformation between the chip and a bare silicon plate in real time. During the measurement, the bonding head applied a constant load to the NCF, and its temperature went up. In order to observe the effect of chip size, NCF deformation was measured at three chip sizes. The amount of deformation of a large-sized chip was found to be less than that of a small-sized chip under the same pressure applied to the chips. This result revealed a limitation of the chip stacking process for large-sized chips using NCF. In addition, variations in bump height or silicon thickness occurring in the LSI manufacturing process were found to cause various problems in the chip stacking process using NCF. These problems were solved using a special bonding tool. Moreover, to suppress voids, the behavior of voids was observed, which found voids remaining in the chip corners. Shaping NCF in the X-shape suppressed these corner voids.


Archive | 2001

Method of mounting chip onto printed circuit board in shortened working time

Shunji Baba; Takatoyo Yamakami; Norio Kainuma; Kenji Kobae; Hidehiko Kira; Hiroshi Kobayashi


Archive | 2002

Method of mounting semiconductor chip

Shunji Baba; Takatoyo Yamakami; Norio Kainuma; Kenji Kobae; Hidehiko Kira; Hiroshi Kobayashi


Archive | 2002

Semiconductor chip element, semiconductor chip element mounting structure, semiconductor chip element mounting device and mounting method

Norio Kainuma; Shunji Baba; Hidehiko Kira; Toru Okada


Archive | 1999

Method of producing a multichip package module in which rough-pitch and fine-pitch chips are mounted on a board

Hidehiko Kira; Kenji Kobae; Norio Kainuma; Naoki Ishikawa; Satoshi Emoto


Archive | 2007

Electronic device, electronic apparatus mounting electronic device, article mounting electronic device, and method for manufacturing electronic device

Hiroshi Kobayashi; Kenji Kobae; Shuichi Takeuchi; Hidehiko Kira


Archive | 1999

Semiconductor bare chip, method of manufacturing semiconductor bare chip and mounting structure of semiconductor bare chip

Hidehiko Kira; Kiyoshi Fukui; Kazuhisa Tsunoi; Shunji Baba


Archive | 2000

Integrated circuit chip supporting and electrically connecting a head slider

Shunji Baba; Hidehiko Kira; Norio Kainuma; Toru Okada


Archive | 2004

Method of forming multi-piled bump

Naoki Ishikawa; Shuichi Takeuchi; Hidehiko Kira

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