Shunji Baba

Development of second-level connection method for large-size CPU package

This paper reports on second-level interconnection development for a large-scale Ball Grid Array (BGA) package. Generally, control of warpage becomes a problem as BGA packages become larger. To solve this problem, the following two measures were executed. The first was adoption of a low-temperature solder, and the second was warpage control using a heat spreader as a fixture. We were able to decrease the reflow temperature to 200°C by applying the low-temperature solder, and the effect was a warp reduction of 200 μm. Moreover, the shape of the heat spreader was optimized through a thermal-stress simulation, obtaining a warp reduction of 100 μm. Verification with a test vehicle was executed, no short/opening was observed, and the results of a thermal cycle test and simulation confirmed there was no problem in reliability.

Low cost flip chip technology for organic substrates

This paper describes outline of the flip chip technology which is used on various kind of substrates (glass-epoxy, flexible Printed Circuit Board, and MCM-L/D). In this technology, Au bumps are formed on the chip I/O pads by wire bonding method, and the bumps are pressed against the substrate pads. The chip is bonded and encapsuled with a thermosetting adhesive, and conductive paste assists mechanical and electrical connection between the Au bumps and the substrate in order to increase the connection reliability. To apply this technology to different types of substrates, we surveyed the deformation characteristic of the substrate pad and the characteristic of the adhesive for encapsulation (adhesion strength and insulation). This technology has been applied to some practical products and the mounting areas of LSI become 1/10 or less compared with existing SMD package approach.