Hidehiro Toyoda

A 25-Gb/s 2.2-W 65-nm CMOS Optical Transceiver Using a Power-Supply-Variation-Tolerant Analog Front End and Data-Format Conversion

A one-chip optical transceiver for board-to-board transmission was developed by integrating an analog frontend (FE) with a data-format-conversion (DFC) block in 65-nm CMOS process technology. It was experimentally demonstrated that this transceiver can convert 10x 6.25-Gb/s electrical signals to 4x 25-Gb/s optical signals with 25% redundancy that improves resilience against possible laser diode (LD) failure. To alleviate degradation of the optical link due to power-supply variations, a power-supply-noise-tolerant 25-Gb/s analog FE (consisting of a TIA with a noise canceller and a fully differential LD driver) is proposed. The noise canceller can keep the power-supply variation below 0.2 mV at frequencies down to 1 MHz, and the fully differential LD driver can keep power-supply current variation below 0.64 mApp/ch, despite a large modulation current of 20 mApp. As for the transmission performance of the transceiver, eye diagrams experimentally confirmed 25-Gb/s and 6.25-Gb/s data-transmission rates. A 25-Gb/s optical-link test on the transceiver demonstrated error-free operation at -6.1-dBm OMA. Moreover, an image-transfer test on the transceiver operating at a data rate of 20 Gb/s through a 100-m multi-mode fiber was demonstrated. Total power consumption of the transceiver (including optics) was 2.2 W at full-channel operation.

100GbE PHY and MAC layer implementations

This article discusses the logical implementation of the media access control and the physical layer of 100 Gb/s Ethernet. The target are a MAC/PCS LSI, supporting MAC and physical coding sublayer, and a gearbox LSI, providing 10:4 parallel lane-width exchange inside an optical module. The two LSIs are connected by a 100 gigabit attachment unit interface, which consists of ten 10 Gb/s lines. We realized a MAC/PCS logical circuit with a low-frequency clock on a FPGA, whose size is 250 kilo LUTs with a 5.7 Mbit RAM, and the power consumption of the gearbox LSI estimated to become 2.3 W.

A 25-Gb/s 2.2-W optical transceiver using an analog FE tolerant to power supply noise and redundant data format conversion in 65-nm CMOS

A one-chip transceiver was developed for optical backplanes by integrating an analog FE with data format conversion in 65-nm CMOS. 10×6.25Gb/s electrical signals were converted to 4×25Gb/s optical signals with 25% redundancy to improve resilience against possible LD failure. To alleviate degradation of the optical link due to power-supply variations, a TIA with a noise canceller and a fully differential LDD are proposed. The noise canceller decreases power-supply variations by 98%. Total power consumption was only 2.2W.

25-Gbps receiver for 100-Gbps ethernet employing cost-effective small coaxial package

We developed a 25-Gbps receiver employing a small, cost effective coaxial package and flexible printed circuits. Our fabrication method for reducing electrical resonance and loss was effectively applied. The fabricated receiver had a 24-GHz 3-dB bandwidth and was successfully operated at 25 Gbps.

100-Gb/s Physical-Layer Architecture for Next-Generation Ethernet

A high-speed physical-layer architecture for Ethernet is described that supports 100-Gb/s throughput and 40-km transmission, making it well suited for next-generation metro-area and intrabuilding networks. Its links comprise 12 x 10-Gb/s synchronized parallel optical lanes. Ethernet data frames are transmitted by coarse wavelength division multiplexing link and bundled optical fibers. Ten of the lanes convey 640-bit data synchronously (64 bits x 10 lanes). One conveys forward error correction code ((132b, 140b) Hamming code), providing highly reliable (BER < 10 -12 ) data transmission, and the other conveys parity data, enabling faultlane recovery. A newly developed 64B/66B code-sequence-based deskewing mechanism is used that provides low-latency compensation for the lane-to-lane skew, which is less than 88 ns. Testing of this physical-layer architecture in a field programmable gate array circuit demonstrated that it can provide 100-Gb/s data communication with a 590k gate circuit, which is small enough for implementation in a single LSI circuit.

Components and Interconnection Technologies for Photonic-Assisted Routers Toward Green Networks

Photonic technology is an important solution to achieve power-saving routers/switches for green networks. As networking is a worldwide matter, and as the power consumed by routers and switches is rapidly increasing, power-efficient green networks have become a subject of great interest. The main issue of green networking is relieving the increasing power consumption, and photonic technologies will be effective for such issue. Photonic technologies are low-power external input/output (I/O) port and internal interconnection subsystem, which contributes to reduce power consumption of routers and switches. For the external I/O port, 100-Gb Ethernet technologies, which use high-speed and low-power optical and electrical CMOS devices, will be described. Also, we describe the power-saving photonic technologies for interconnection subsystems for network equipments. This optical interconnection (optical backplane) technology also requires optical and electrical devices, which are compact in size, high speed, and operate at low power. This interconnection realizes a highly energy efficient router/switch with advanced network functions.

A 100-Gb-Ethernet subsystem for next-generation metro-area network

An ultra high-speed Ethernet subsystem, which realizes 100-Gb/s throughput and transmission up to 40 km, is examined for next-generation metro-area networks. A parallel link of 12 10-Gb/s synchronized parallel optical lanes is proposed. The 10 optical lanes are used to transmit 10-bit parallel data. The one of redundant lanes transmits a forward error correction code ((132b, 140b) Hamming code) to achieve highly-reliable (BER < 10-12) data transmission, and the other lane transmits a parity data used for the fault-lane recovery. Here, a 64B/66B code-sequence-based de-skewing mechanism is proposed, and its effectiveness to realize low-latency compensation of the inter-lane skew (< 80 ns) is shown. We have implemented the 100-Gb-Ethernet interface architectures into FPGA circuits, and confirmed the performance of 100 Gb/s data communication with compact 385-kgates circuit size, which is practically small for implementation in a single LSI circuit.

A 400-Gb/s and Low-Power Physical-Layer Architecture for Next-Generation Ethernet

A new 400-Gb/s (100-Gb/s×4) physical-layer architecture for the next-generation Ethernet-using 100-Gb/s serial (optical single wavelength) transmission-is proposed. For the next-generation 400-Gb/s Ethernet, there are additional requirements from the market, such as power reduction and further compactization in addition to attaining even higher transmission speed. To meet these requirements, a 100-Gb/s×4 physical-layer architecture is proposed. This architecture uses a 100-Gb/s serial (optical single wavelength) transmission Ethernet and low-power control technologies, which include transmission-capacity-degeneracy control for multi-lane transmission Ethernet. These technologies were implemented on a 100-Gb/s serial (optical single wavelength) transmission Ethernet using a field-programmable gate array (FPGA). Experimental evaluation of this implementation demonstrates the feasibility of low-power and fault-tolerant 400-Gb/s Ethernet.

Wavelength switching method combined with downstream queue monitoring per ONU for λ-tunable WDM/TDM-PON

We propose a wavelength switching method combined with queue status monitoring per ONU to improve latency of λ-switching ONU while frame loss is prevented for λ-tunable WDM/TDM-PON. Latency degradation by λ-switching of less than 4.1 ms was achieved.

A 100 Gb/s and High-Reliable Physical-Layer Architecture for VSR and Backplane Ethernet

A high-throughput and high-reliable physical-layer architecture for very-short-reach (VSR) and backplane Ethernet applications was developed. VSR and backplane networks provide 100-Gb/s data transmission between blade servers and LAN switches. This architecture supports 100-Gb/s-throughput, high-reliability, and low-latency data transmission, making it well suited to VSR and backplane applications for inter-LAN-switch and intra-cabinet networks. Its links comprise ten 10-Gb/s highspeed serial lanes. Payload data are transmitted by a ribbon fiber and a copper cable for VSR applications and by copper channels for the backplane board. Ten lanes convey Ethernet data frames and parity data of forward-error correction code (newly developed (544, 512) code FEQ, providing highly reliable (BER<lE-22) data transmission with a burst-error correction with low latency (i.e., 29.0 ns on the transmitter (Tx) side and 104.4 ns on the receiver (Rx) side). A 64B/66B code-sequence-based skew compensation mechanism, which provides low-latency compensation for the lane-to-lane skew, is used for multi-lane serial transmission. Testing an ASIC with this physical-layer architecture showed that it can provide 100-Gb/s data transmission with a 747-kgate circuit, which is small enough to be implemented in a single LSI. Furthermore in this paper, insufficient FEC rate in past report was solved, and a technique for improving reliability of the above compensation mechanism was proposed.