Hidekazu Terai
Ritsumeikan University
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Publication
Featured researches published by Hidekazu Terai.
information reuse and integration | 2007
Hidekazu Terai
The traveling salesman problem (TSP) is one of the most important problems in combinational optimization. Many works have done for this problem using ant colony optimization (ACO). The ACO is one of the most powerful optimization methods that combines distributed computation, auto-catalysis (positive feedback) and constructive greedy heuristic in finding optimal solutions for combinational optimization problems. Most of these previous works deal with software processing. However, ACO has the inherent problem of requiring substantial processing time. Therefore, the dedicated ACO hardware becomes important when applying ACO to combinational problems. In this paper, we propose a new hardware architecture for ACO. No previous studies have, to our knowledge, applied ACO hardware to TSP, as this study does using the proposed architecture. Experimental results to evaluate the proposed algorithm show improvement comparison with software processing.
international symposium on circuits and systems | 2004
Tetsuya Imai; Masaya Yoshikawa; Hidekazu Terai; Hironori Yamauchi
This paper presents the VLSI processor architecture for real-time processing of genetic algorithm (GA). GA, which is widely known a general-purpose optimization method, has essential difficulties in its huge computation time and a premature convergence. As a new approach to these difficulties, it is introduced to implement distributed GA on VLSI multiprocessors (GA processor). VLSI implementation of a processor-element (PE) indicates that a PE can be 130 times faster than conventional software processing. Moreover, parallel computer simulation demonstrates that GA processor, which connects a suitable number of PE with a newly proposed hierarchical ring topology, can provide scalability according to a given problem.
computer science and information engineering | 2009
Hidekazu Terai
This paper discusses a new route selection algorithm and particularly focuses as follows: (1) A hybrid technique which combines Genetic Algorithm with Dijkstra Algorithm is introduced to achieve high quality route guidance. (2) The proposed car navigation system enables to find a route which has several passing points before arriving at the final destination. (3) New genetic operations for car navigation system are introduced not to generate a lethal gene. Experiments using map data prove the effectiveness of the proposed car navigation system.
international conference on smart manufacturing application | 2008
Masahiro Fukui; Hidekazu Terai
The Ant Colony Optimization (ACO) is one of the most powerful optimization methods. Many works have done for combinational optimization problems using ACO. The main search mechanism of ACO is pheromone communication of each ant. Most of these previous works adopt the same pheromone control algorithm. In this paper, we proposed a new pheromone control algorithm to improve the search performance and to reduce the processing steps. No previous studies have, to our knowledge, applied the additional pheromone control. Experimental result to evaluate the proposed algorithm shows improvement comparison with normal pheromone control algorithm.
international conference on acoustics, speech, and signal processing | 2002
Tetsuya Imai; Masaya Yoshikawa; Hidekazu Terai; Hironori Yamauchi
Genetic Algorithm (GA) is widely known as a general-purpose optimization method, which can provide sub-optimum solutions for various. optimization problems by means of modeling genetic evolutionary process of creatures. Several essential difficulties exist in GA, however, with regard to large amount of computation time, premature convergence in early stage of evolution and proper adjustment of many GA parameters. In order to overcome the difficulties of GA, this paper describes the architecture of a scalable and high-speed GA processor, which is characterized by hardware-oriented approach based on Distributed GA, optimized hierarchic pipelines for high-speed evolutions and flexible genetic operations corresponding to a given problem. Furthermore, this paper also describes VLSI implementation of a processor-element to verify feasibility of our proposed architecture for applications.
international conference on mechatronics and automation | 2005
Masaya Yoshikawa; Hidekazu Terai
Deep-sub-micron technology (DSM) of 0.18 micron and below enable the integration of logical circuits having more than 10 million gates. In such a DSM technology, layout design has become the most important design phase. This paper discusses a novel performance-driven placement technique. The proposed algorithm based on hybrid genetic algorithms (GA) has a two-level hierarchical structure. For selection control, new objective functions are introduced for improving power consumption, interconnect delay, wire congestion and chip area. Experimental results show improvement comparison with commercial EDA tool.
midwest symposium on circuits and systems | 2007
Hidekazu Terai
This route selection is an important problem for a car navigation system. In general car navigation system, the Dijkstra algorithm (DA) is used as route selection algorithm. From the viewpoint of practical convenience of the driver, we assume a route selection model that a driver must visit at shops (for example, restaurant) on the way to a destination, but it is not necessary for these shops to be specific shops. Several studies have dealt with conducted this problem using virus genetic algorithm (VGA). However, the VGA requires much calculation time, because VGA is multipoint search algorithm. In this paper, we propose an architecture for high-speed car navigation system based on VGA. Moreover, the route guidance function for sightseeing is newly added to the proposed architecture. The proposed architecture, implemented on the field-programmable gate array (FPGA), achieves high-speed processing. Measurement evaluating the proposed architecture demonstrated speeds 20 times greater than software processing.
software engineering research and applications | 2005
Masaya Yoshikawa; Hidekazu Terai
Deep-sub-micron technology (DSM) of 0.18 micron and below enable the integration of logical circuits having more than 10 million gates. In such a DSM technology, layout design has become the most important design phase. This paper discusses a novel congestion-driven placement technique based on asynchronous parallel genetic algorithm. The proposed algorithm has a two-level hierarchical structure. For selection control, new objective functions are introduced for wire congestion and chip area. Moreover, the two kind of parallel processing suitable for hierarchical processing is introduced for reduction of run time. Experimental results show improvement comparison with conventional layout technique.
intelligent data acquisition and advanced computing systems: technology and applications | 2005
Masaya Yoshikawa; Masahiro Fukui; Hidekazu Terai
The floorplanning problem is an essential design step in VLSI layout design and it is how to place rectangular modules as density as possible. In this paper, we proposed a novel performance driven floorplanning technique. The proposed algorithms based on genetic algorithm (GA) is adopted to a sequence pair. The GA is one of the most powerful optimization methods based on the mechanics of natural evolution. However, the problem of the processing time stemming from a population based search exits in GA. In order to reduce the processing time, a novel technique of collaboration of software (SW) and hardware(HW) also is introduced. Experimental results evaluating the proposed algorithm are shown good performance.
european conference on circuit theory and design | 2005
Masaya Yoshikawa; Hidekazu Terai
This paper discusses the architecture for high-speed floorplanning using sequence pair representation based on hybrid genetic algorithms. The hybrid optimization of GA and SA in the proposed architecture realized searching not only globally but also locally. To keep general purpose, the proposed architecture is flexible for many genetic operations on GA and achieves high speed processing by adopting dedicated hardware. Furthermore, the proposed architecture realized not only the pipeline on evaluation phase, but also the pipeline on evolutionary phase on GA. Simulation results evaluating the proposed architecture are shown to the effectiveness.