Masaya Yoshikawa

VLSI processor architecture for real-time GA processing and PE-VLSI design

This paper presents the VLSI processor architecture for real-time processing of genetic algorithm (GA). GA, which is widely known a general-purpose optimization method, has essential difficulties in its huge computation time and a premature convergence. As a new approach to these difficulties, it is introduced to implement distributed GA on VLSI multiprocessors (GA processor). VLSI implementation of a processor-element (PE) indicates that a PE can be 130 times faster than conventional software processing. Moreover, parallel computer simulation demonstrates that GA processor, which connects a suitable number of PE with a newly proposed hierarchical ring topology, can provide scalability according to a given problem.

Scalable GA processor architecture and its implementation of processor-element

Genetic Algorithm (GA) is widely known as a general-purpose optimization method, which can provide sub-optimum solutions for various. optimization problems by means of modeling genetic evolutionary process of creatures. Several essential difficulties exist in GA, however, with regard to large amount of computation time, premature convergence in early stage of evolution and proper adjustment of many GA parameters. In order to overcome the difficulties of GA, this paper describes the architecture of a scalable and high-speed GA processor, which is characterized by hardware-oriented approach based on Distributed GA, optimized hierarchic pipelines for high-speed evolutions and flexible genetic operations corresponding to a given problem. Furthermore, this paper also describes VLSI implementation of a processor-element to verify feasibility of our proposed architecture for applications.

A novel performance-driven placement based on hybrid genetic algorithm

Deep-sub-micron technology (DSM) of 0.18 micron and below enable the integration of logical circuits having more than 10 million gates. In such a DSM technology, layout design has become the most important design phase. This paper discusses a novel performance-driven placement technique. The proposed algorithm based on hybrid genetic algorithms (GA) has a two-level hierarchical structure. For selection control, new objective functions are introduced for improving power consumption, interconnect delay, wire congestion and chip area. Experimental results show improvement comparison with commercial EDA tool.

Asynchronous parallel genetic algorithm for congestion-driven placement technique

Deep-sub-micron technology (DSM) of 0.18 micron and below enable the integration of logical circuits having more than 10 million gates. In such a DSM technology, layout design has become the most important design phase. This paper discusses a novel congestion-driven placement technique based on asynchronous parallel genetic algorithm. The proposed algorithm has a two-level hierarchical structure. For selection control, new objective functions are introduced for wire congestion and chip area. Moreover, the two kind of parallel processing suitable for hierarchical processing is introduced for reduction of run time. Experimental results show improvement comparison with conventional layout technique.

Performance-Driven Floorplanning Technique Based on Collaboration of Software and Hardware

The floorplanning problem is an essential design step in VLSI layout design and it is how to place rectangular modules as density as possible. In this paper, we proposed a novel performance driven floorplanning technique. The proposed algorithms based on genetic algorithm (GA) is adopted to a sequence pair. The GA is one of the most powerful optimization methods based on the mechanics of natural evolution. However, the problem of the processing time stemming from a population based search exits in GA. In order to reduce the processing time, a novel technique of collaboration of software (SW) and hardware(HW) also is introduced. Experimental results evaluating the proposed algorithm are shown good performance.

Hybrid genetic algorithm engine for high-speed floorplanning

This paper discusses the architecture for high-speed floorplanning using sequence pair representation based on hybrid genetic algorithms. The hybrid optimization of GA and SA in the proposed architecture realized searching not only globally but also locally. To keep general purpose, the proposed architecture is flexible for many genetic operations on GA and achieves high speed processing by adopting dedicated hardware. Furthermore, the proposed architecture realized not only the pipeline on evaluation phase, but also the pipeline on evolutionary phase on GA. Simulation results evaluating the proposed architecture are shown to the effectiveness.

A novel timing-driven placement using genetic algorithm

This paper discusses a novel timing driven placement technique using Genetic Algorithms (GAs), and focuses particularly on the following points: (1) The algorithm has two-level hierarchical structure consisting of outline placement, which partitions a chip area into several areas, and detail placement, which determines cell positions in the partitioned area. The procedure for determining optimal cell positions is then explained. (2) For selection control, which is one of the genetic operations, new multi-objective functions are introduced at each phase for improving delay, reducing congestion and dispersing power. Results show improvement of 14.2% for the worst path delay on average.

The new DFM approach based on a genetic algorithm

As scaling has continued for more than 20 years, it has yielded faster and denser chips with ever increasing functionality. With recent advances in technology, the number of transistors mounted on a VLSI chip is about 10 million gates. In such advanced technology, device feature sizes have become increasingly smaller than the wavelength of light used by the available optical lithography equipment. Therefore, a design for manufacturability (DFM) approach has become the most important factor in the design of LSI. In this article, we propose a new DFM approach as the target for the next generation in the layout design phase. Simulation results evaluating the proposed algorithm show good performance.

Apriori, Association Rules, Data Mining,Frequent Itemsets Mining (FIM), Parallel Computing

The job-shop scheduling problem is concerned with allocating limited resources to operations over time. Although the job shop scheduling has an important role in various fields, it is one of the most difficult problems in combinational optimization. In this paper, we propose a new scheduling technique that combines Ant Colony Optimization (ACO) with GT method in order to realize effective scheduling. ACO approach has been applied recently to several combinational optimization problems, e.g., TSP and scheduling problem. However, no studies have ever seen the approach of applying hybrid ACO to job-shop problems. Experimental results using benchmark data show improvement comparison with a conventional scheduling technique.

Design of LSI for crossover operation based on sequence pair

The floorplanning problem, which is an essential design step in VLSI layout design, consists of determining the placement of rectangular modules as densely as possible. Many studies have been carried out on this problem using sequence pairs based on genetic algorithms (GAs). However, the GA-based method generally requires a great amount of computation time. Therefore, we propose the architecture for high speed floorplanning using a sequence pair based on GA. In this paper, the proposed architecture is implemented on LSI, and achieves high speed processing