Hironori Yamauchi

Architecture and implementation of a highly parallel single-chip video DSP

The architecture of a single-chip video DSP capable of attaining a maximum performance of 300-MOPS (mega operations per second) using 0.8- mu m CMOS technology is described. The DSP is designed for the many applications regarding p*64 kb/s single-board video codecs based on DSPs that have roughly ten times the performance of conventional DSPs. Highly parallel architectures that allow four pipelined processing units to be integrated into one chip are studied extensively. The authors consider data path configurations, program sequencing control, and microinstructions that effectively support multiple pipeline processing. A prototype DSP is fabricated using 0.8- mu m CMOS technology, and some performance evaluations are presented. >

An 18-bit floating-point signal processor VLSI with an on-chip 512W dual-port RAM

A brand-new floating-point Digital Speech Signal Processor VLSI (DSSP), intended for a wide range of applications in speech processing, is developed. For speech applications, a wide dynamic range vector operation that includes FFT and complex arithmetic is necessary in executing a highly-complicated coding algorithm that treats a large amount of windowed data collectively. To meet this requirement, the floating-point data format and hardware architecture is extensively studied. The DSSP, which is fabricated using 2.5um CMOS technology, completes almost all the floating-point operations within a 150ns machine-cycle.

Signal and noise separation in medical diagnostic system based on independent component analysis

The possibility to study graphic recording (PCG -Phonocardiography) of auscultator findings is a helpful diagnostic tool for the clinician and forms the basis of early detection of the heart problems. Due to its dispersed nature and overlapping with breathing sounds Heart Sound Signals (HSS) is difficult to detect and comprehend in conventional PCG. We present a Hardware system utilizing Frequency-Domain Independent Component Analysis (ICA) deploying Direction of Arrival (DOA) and Beamforming (BF) techniques for the suppression of noise which will enhance the quality of HSS and aid the physicians. Such techniques of HSS extraction have been rarely studied in the past.

A 50ns floating-point signal processor VLSI

A high-speed programmable digital signal processor VLSI with an 18-bit floating-point architecture and a 32-bit micro-instruction has been fabricated using 1.2µm CMOS technology. The device contains 280k transistors and executes every floating-point operation within a 50ns machine-cycle. The architecture differs from that of the DSSP (Digital Speech Signal Processor), reported previously, in its high-speed parallel pipeline structure, 16k-byte on-chip micro-program ROM, floating-point ALU capable of 50ns operation, as well as in its enhanced DSP instruction set.

VLSI processor architecture for real-time GA processing and PE-VLSI design

This paper presents the VLSI processor architecture for real-time processing of genetic algorithm (GA). GA, which is widely known a general-purpose optimization method, has essential difficulties in its huge computation time and a premature convergence. As a new approach to these difficulties, it is introduced to implement distributed GA on VLSI multiprocessors (GA processor). VLSI implementation of a processor-element (PE) indicates that a PE can be 130 times faster than conventional software processing. Moreover, parallel computer simulation demonstrates that GA processor, which connects a suitable number of PE with a newly proposed hierarchical ring topology, can provide scalability according to a given problem.

Detecting mass and its region in mammograms using mean shift segmentation and Iris Filter

In recent years, many Computer Aided Diagnosis (CAD) systems are suggested. Those systems can diagnose instead of a doctor, thus they are expected to reduce heavy burdens on the doctor during screening. The purpose of this study is to improve detection sensitivity for masses reducing the number of false positives as well as to extract mass regions accurately. In the proposed method, we focused on brightness and density of masses, thus we applied mean shift segmentation. After the segmentation, we obtained concentration of gradient vectors using Iris Filter and detected mass regions. According to the field test with a doctor, the proposed system was tested with 398 mammograms containing 193 masses. In the result of a performance test, a sensitivity of 81% was obtained at 5.0 false positives per image and 75% masses are detected at Area Overlap Measure (AOM) of more than 60%.

Scalable GA processor architecture and its implementation of processor-element

Genetic Algorithm (GA) is widely known as a general-purpose optimization method, which can provide sub-optimum solutions for various. optimization problems by means of modeling genetic evolutionary process of creatures. Several essential difficulties exist in GA, however, with regard to large amount of computation time, premature convergence in early stage of evolution and proper adjustment of many GA parameters. In order to overcome the difficulties of GA, this paper describes the architecture of a scalable and high-speed GA processor, which is characterized by hardware-oriented approach based on Distributed GA, optimized hierarchic pipelines for high-speed evolutions and flexible genetic operations corresponding to a given problem. Furthermore, this paper also describes VLSI implementation of a processor-element to verify feasibility of our proposed architecture for applications.

A highly-parallel single-chip DSP architecture for video signal processing

The architecture of a newly developed highly parallel pipeline DSP that achieves over 300 MOPS/LSI programming capability is presented. This programmable single-chip DSP is designed for application to a variety of different single-board moving image codecs, which require a DSP with roughly 10 times the power of conventional single pipeline unit architecture DSPs. Assuming 0.8- mu m CMOS technology, a single-chip DSP architecture integrating four sets of pipeline processing units was extensively studied. The DSP configuration and noble techniques enabling efficient operation of plural pipeline processing units are described. Evaluation of the performance of the DSP is also presented.<<ETX>>

Local Gabor directional pattern histogram sequence (LGDPHS) for age and gender classification

This paper proposes means to classify age and gender in facial images using novel features. First, Gabor magnitude pictures are obtained by convolving the image with Gabor filters in several scale and orientation, followed by encoding with Local Directional Pattern (LDP) operator which enhances information. Then, the maps are divided into several blocks, and histograms are extracted from each block. The histograms are concatenated to a vector. Then Principal Component Analysis (PCA) is used to reduce the dimensions. Finally, the feature vector is classified by Support Vector Machine (SVM). The experimental results demonstrate that the algorithm proposed in this paper is effective method, compared to other similar methods.

Reliability enhancements for the direct wafer exposure electron beam system EB60

Based on the exposure architecture of ‘‘EB60,’’ intensive effort has been made to achieve an integrated system that is both reliable and easy to adjust. First, the central processing unit (CPU) and network structure have been modified to exploit an open system environment and to tighten communication between the e‐beam and computer aided design (CAD) systems. Exposure data are transferred over a high‐speed optical cable directly from the remotely located CAD resident host CPU. Five custom larger scale integrated circuits (LSIs) have been designed and implemented. A complimentary metal–oxide semiconductor LSI (22 Kgates) that performs general linear matrix functions in 60 ns has been applied to minor‐field‐deflector, shaping‐deflector, shot‐time, stage movement, and overlay coordinate corrections. A shot control super self‐aligned transistor (SST) LSI (2.5 Kgates), which covers all functions operating at 400 MHz, has eliminated the tedious adjustment of emitter coupled logic (ECL) circuits. Taken together,...