Hideki Hatakeyama

A low phase noise LC-VCO with a high-Q inductor fabricated by wafer level package technology

This paper presents a CMOS voltage controlled oscillator (VCO) with a high-Q inductor fabricated by using a commercial wafer-level-package (WLP) technology. A new topology suitable for CMOS VCOs with high-Q WLP inductors is proposed. Measured Q of a WLP inductor is 40 in differential mode at around 1.9 GHz. A phase noise is -134.4 dBc/Hz at a 1 MHz offset for 1.9 GHz carrier frequency, and a FoM is -193 dBc/Hz. The VCO with the WLP inductor improves a phase noise of 6.4 dB as compared to VCOs with conventional on-chip inductors.

A Low-Power Low-Phase-Noise CMOS VCO using RF SiP Technology

This paper presents a feasibility study on VCO using RF SiP technology, which is an RF application of stacked SiP. An off-chip inductor is implemented in a separated chip, and measured Q factor is 130. A phase noise is -119 dBc/Hz at 1 MHz offset for a 5.84-GHz carrier frequency, and frequency tuning range is 5.73 GHz-5.95 GHz. Power consumption is 1.93 mW, and 180 nm CMOS process is utilized. FOM is -192dBc/Hz.

Low-loss and compact millimeter-wave balun on Si

We designed and fabricated low-loss and compact microstrip line and Marchand balun composed of thick Cu and thick resin on Si substrate for millimeter-wave applications. An attenuation constant α and Q of the fabricated microstrip line are 0.17 dB/mm and 52 at 60GHz, respectively. The insertion loss and the core size of the fabricated balun are 0.6 dB at 60 GHz and 300 µm × 450 µm, respectively, which are the lowest and the smallest among the millimeter-wave baluns ever reported, to our knowledge.

Low-loss millimeter-wave passives on Si

We proposed a 60 GHz millimeter-wave platform on which several low-loss passive devices are integrated and attached to CMOS-LSI using flip-chip technology. To confirm the advantage of the platform, we fabricated passive devices of microstrip lines and a bandpass filter. We successfully obtained a low attenuation loss of 0.2 dB/mm at 60 GHz in the microstrip line. We also achieved low-loss and highly-selective bandpass filter.

A Low-Power Differential Transmission Line Interconnect Using Wafer Level Package Technology

This paper proposes a low-power on-chip transmission line interconnect (TLI) using wafer level package (WLP) technology. A 0.18 mum Si CMOS process was used to fabricate a transmitter (Tx) and a receiver (Rx). The prototype TLI with a transmission line in WLP has about 40% smaller power consumption than that with a transmission line in multilevel interconnects.