Noboru Ishihara

A sub-1mw 5.5-GHz PLL with digitally-calibrated ILFD and linearized varactor for low supply voltage operation

This paper proposes an ultra-low-power 5.5GHz PLL which employs a divide-by-4 injection-locked frequency divider (ILFD) and linearity-compensated varactor for low supply voltage operation. The digital calibration circuit is introduced to control the ILFD frequency automatically. The proposed varactor, which applies a forward-body-bias (FBB) technique, is employed for linear-frequency-tuning under the power supply of 0.5 V. The proposed PLL was fabricated in 65 nm CMOS. With a 34.3-MHz reference, it shows a 1-MHz-offset phase noise of -106 dBc/Hz, a reference spur level lower than -65 dBc, and the total power consumption of 950μW at 5.5 GHz.

A Novel Direct Injection-Locked QPSK Modulator Based on Ring VCO in 180 nm CMOS

A novel quadrature phase-shift keying (QPSK) modulator that employs injection locking for the phase modulation as well as the phase-locked clock generation is presented. By using the proposed simple modulator based on a ring voltage-controlled oscillator (VCO), many blocks in the conventional QPSK modulators are removed, and the total area can be reduced.The proposed QPSK modulator was fabricated in a 180 nm CMOS, and occupies an area of 0.024 mm2 . The modulator achieves measured error vector magnitude (EVM) of 8.23% at 50.8 Mb/s under QPSK modulation with the total power consumption of lower than 6 mW from a 1.8 V power supply.

An inductorless injection-locked PLL with 1/2- and 1/4-integral subharmonic locking in 90 nm CMOS

An inductorless PLL with 1/2- and 1/4-integral as well as integral subharmonic injection locking is realized, which can solve tradeoff between the selectable frequency step and phase noise of injection-locked PLLs (ILPLLs). The proposed ILPLL was fabricated in 90 nm CMOS process (PLL area: 0.083 mm2, tuning range: 1.1-2.0 GHz). For a 80 MHz reference, it shows that the 1-MHz-offset phase noise is -106 dBc/Hz at 1.8 GHz (= 11.25 × 160 MHz) with injection. A 15-dB reduction is achieved, compared with that in the case without injection.

A Multi-Band Quadrature Clock Generator With High-Pass-Filtered Pulse Injection Technique

A high-pass-filtered (HPF) pulse injection technique is proposed to reduce spurs near the carrier signal due to injection locking. By using this technique, a multi-band quadrature clock generator consisting of a wide-frequency range injection-locked PLL and a frequency-selectable local buffer is demonstrated. The proposed clock generator was fabricated in a 65 nm CMOS. For a 100 MHz reference, the circuit can output 1.0, 2.0, and 4.0 GHz quadrature outputs with an eight-phase VCO and the buffer. It shows an 1 MHz-offset phase noise -105 dBc/Hz and a reference spur level of -50 dBc at 2.0 GHz, with enabling HPF pulse injection. The total power consumption is lower than 32 mW at 4 GHz.

Planar Solenoidal Inductor in Radio Frequency Micro-Electro-Mechanical Systems Technology for Variable Inductor with Wide Tunable Range and High Quality Factor

A planar solenoidal inductor for the realization of a variable inductor with a wide tunable range and a high quality factor (Q-factor) is proposed in this work. Prototype inductors are designed and fabricated using a two-metal micro-electro-mechanical systems (MEMS) process to demonstrate the potential use of the tunability of the inductance and the Q-factor. Inductance tuning from 1 to 3.3 nH was achieved and the tunability obtained was as high as 230% at 2 GHz. A Q-factor of more than 20 was observed in the frequency range of 2.5 to 6 GHz.

An Inductorless Cascaded Phase-Locked Loop with Pulse Injection Locking Technique in 90 nm CMOS

An inductorless phase-locked loop with subharmonic pulse injection locking was realized (PLL narea: 0.11u2009mm2) by adopting 90u2009nm Si CMOS technology. The proposed circuit is configured with two cascaded PLLs; one of them is a reference PLL that generates reference signals to the other one from low-frequency external reference signals. The other is a main PLL that generates high-frequency output signals. A high-frequency half-integral subharmonic locking technique was used to decrease the phase noise characteristics. For a 50 MHz input reference signal, without injection locking, the 1 MHz offset phase noise was −88u2009dBc/Hz at a PLL output frequency of 7.2u2009GHz (= 144 × 50u2009MHz); with injection locking, the noise was −101u2009dBc/Hz (spur level: −31u2009dBc; power consumption from a 1.0u2009V power supply: 25u2009mW).

A process-scalable RF transceiver for short range communication in 90 nm Si CMOS

This paper presents the RF CMOS transceiver that potentially has the process scalability in terms of area and supply voltage. The proposed transceiver does not contain any inductor and employs inverter-based topology for attaining scalability and large voltage headroom. The prototype transceiver for short-range communication fabricated in 90nm Si CMOS process has area of 0.2mm2 and achieves 500 Mb/s communication at 1V supply voltage. The transmitter with the new linearity compensation technique provides EVM of less than -28 dB at -5dBm output from 0.5 to 2.5 GHz range. The receiver employs active peaking and cherry-hooper techniques and realizes sensitivity of -60dBm and dynamic range of 50 dB at 1 GHz.

Challenges in integration of diverse functionalities on CMOS

We introduce “Wafer Shuttle” that is suitable for integration of diverse functionalities. CMOS/MEMS design flow and environment based on SPICE is discussed. It is pointed out that modeling will be important to promote the R&D of MEMS/CMOS and/or diverse-functionalities integration on CMOS.

An Inverter-Based Wideband Low-Noise Amplifier in 40 nm Complementary Metal Oxide Semiconductor

Multistandard RF chips have been highly demanded for multipurpose wireless applications. However, in RF circuits, a low-noise amplifier (LNA) plays an important role in determining the receivers performance. In this paper, we present a scalable wideband LNA based on complementary metal oxide semiconductor (CMOS) inverters, employing two bandwidth expansion techniques to achieve a large bandwidth without using inductors. Fabricated by the 40 nm CMOS process, the LNA attains 0.1–8.0 GHz of flat bandwidth with S21=17.5 dB and S11≤-10 dB. The minimum NF measured is 5.1 dB and the power consumption is 14.3 mW at 1.3 V. The LNA core circuit is as small as 0.001 mm2 since no large passive device is used. A study of LNA scalability has been conducted by comparing the performances of circuits with the same topology fabricated by the 65, 90, and 180 nm CMOS processes.

An RF energy harvesting power management circuit for appropriate duty-cycled operation

In this study, we present an RF energy harvesting power management unit (PMU) for battery-less wireless sensor devices (WSDs). The proposed PMU realizes a duty-cycled operation that is divided into the energy charging time and discharging time. The proposed PMU detects two types of timing, thus, the appropriate timing for the activation can be recognized. The activation of WSDs at the proper timing leads to energy efficient operation and stable wireless communication. The proposed PMU includes a hysteresis comparator (H-CMP) and an RF signal detector (RF-SD) to detect the timings. The proposed RF-SD can operate without the degradation of charge efficiency by reusing the RF energy harvester (RF-EH) and H-CMP. The PMU fabricated in a 180 nm Si CMOS demonstrated the charge operation using the RF signal at 915 MHz and the two types of timing detection with less than 124 nW in the charge phase. Furthermore, in the active phase, the PMU generates a 0.5 V regulated power supply from the charged energy.