Hideki Horii

A novel cell technology using N-doped GeSbTe films for phase change RAM

The Ge/sub 2/Sb/sub 2/Te/sub 5/ (GST) thin film is well known to play a critical role in PRAM (Phase Change Random Access Memory). Through device simulation, we found that high-resistive GST is indispensable to minimize the writing current of PRAM. For the first time, we tried to increase the GST resistivity by doping nitrogen. Doping nitrogen to GST successfully reduced writing current. Also, the cell endurance has been enhanced with grain growth suppression effect of dopant nitrogen.

Highly manufacturable high density phase change memory of 64Mb and beyond

Highly manufacturable 64Mbit PRAM has been successfully fabricated using N-doped Ge/sub 2/Sb/sub 2/Te/sub 5/ (GST) and optimal GST etching process. Using those technologies, it was possible to achieve the low writing current of 0.6 mA and clear separation between SET and RESET resistance distributions. The 64Mb PRAM was designed to support commercial NOR flash memory compatible interfaces. Therefore, the fabricated chip was tested under the mobile application platform and its functionality and reliability has been evaluated by operation temperature dependency, disturbance, endurance, and retention. Finally, it was clearly demonstrated that high density PRAM can be fabricated in the product level with strong reliability to produce new nonvolatile memory markets.

Full integration and reliability evaluation of phase-change RAM based on 0.24 /spl mu/m-CMOS technologies

We have fully integrated a nonvolatile random access memory by successfully incorporating a reversibly phase-changeable chalcogenide memory element with MOS transistor. As well as basic characteristics of the memory operation, we have also observed reliable performances of the device on hot temperature operation, endurance against repetitive phase transition, writing imprint, reading disturbance and data retention.

Highly scalable on-axis confined cell structure for high density PRAM beyond 256Mb

We firstly fabricated on-axis confined structure and evaluated based on 64Mb PRAM with 0.12/spl mu/m-CMOS technologies. Ge/sub 2/Sb/sub 2/Te /sub 5/ was confined within small pore, which resulted in low writing current of 0.4mA. The pore is on-axis with upper and lower contacts, which leads to good scalability of PRAM above 256Mb. The confined structure was relatively insensitive to small cell edge damage effect. The on-axis confined structure is a promising candidate for high density PRAM due to low writing current, good scalability, and insensitiveness to edge damage.

A 20nm 1.8V 8Gb PRAM with 40MB/s program bandwidth

Phase-change random access memory (PRAM) is considered as one of the most promising candidates for future memories because of its good scalability and cost-effectiveness [1]. Besides implementations with standard interfaces like NOR flash or LPDDR2-NVM, application-oriented approaches using PRAM as main-memory or storage-class memory have been researched [2-3]. These studies suggest that noticeable merits can be achieved by using PRAM in improving power consumption, system cost, etc. However, relatively low chip density and insufficient write bandwidth of PRAMs are obstacles to better system performance. In this paper, we present an 8Gb PRAM with 40MB/s write bandwidth featuring 8Mb sub-array core architecture with 20nm diode-switched PRAM cells [4]. When an external high voltage is applied, the write bandwidth can be extended as high as 133MB/s.

An edge contact type cell for Phase Change RAM featuring very low power consumption

In this paper, the Phase Change Random Access Memory (PRAM, also known as Ovonic Unified Memory-OUM) cell, which has an extremely small and reproducible contact area and improved thermal environment, was fabricated and electrically characterized. The memory cell successfully operates with 30 ns pulses of 0.20 mA for RESET (high resistive) state and 0.13 mA for SET (low resistive) state. This is the best record of the published data.

A comparative study on the electrical conduction mechanisms of (Ba0.5Sr0.5)TiO3 thin films on Pt and IrO2 electrodes

Electrical conduction mechanisms for Pt/(Ba0.5Sr0.5)TiO3 (BST)/Pt, IrO2/BST/IrO2, and Pt/BST/IrO2 capacitors were studied. The Pt/BST/Pt capacitor shows a Schottky emission behavior with interface potential barrier heights of about 1.5–1.6 eV. The barrier height is largely determined by the surface electron trap states of the BST. The IrO2/BST interface shows an ohmic contact nature due to the elimination of the surface trap states as the result of the formation of strong chemical bonds between the IrO2 and BST which results in the Poole–Frenkel emission conduction mechanism. Pt/BST/IrO2 capacitor shows Schottky emission behavior and a positive temperature coefficient of resistivity (PTCR) effect depending on the bias polarity. The electron trap states at the Pt/BST interface and the positive space charges within the carrier depletion layer result in the PTCR effect.

Writing current reduction for high-density phase-change RAM

By developing a chalcogenide memory element that can be operated at low writing current, we have demonstrated the possibility of high-density phase-change random access memory. We have investigated the phase transition behaviors as a function of various process factors including contact size, cell size and thickness, doping concentration in chalcogenide material and cell structure. As a result, we have observed that the writing current is reduced down to 0.7 mA.

Preparation and characterization of iridium oxide thin films grown by DC reactive sputtering

Iridium oxide ( IrO2) thin films were successfully grown by a DC magnetron reactive sputtering method. It was found that the crystalline nature and morphology of IrO2 films were strongly dependent on the oxygen partial pressure, total pressure and growth temperature. The growth of IrO2 is well explained by the generic curve for the total pressure as a function of O2 content. The films showed good barrier performance between Pt and poly-Si up to 750° C. A 40-nm-thick Ba0.5Sr0.5TiO3 film was grown by RF magnetron sputtering on the Pt/IrO2/poly-Si electrode. The leakage current density and dielectric constant of a Pt/Ba0.5Sr0.5TiO3/Pt capacitor on the IrO2/poly-Si electrode were comparable to those of the capacitor on a SiO2/Si substrate. However, an additional ohmic layer was required to prevent the formation of a SiO2 layer between the IrO2 and poly-Si.

Preparation and Electrical Properties of SrTiO3 Thin Films Deposited by Liquid Source Metal-Organic Chemical Vapor Deposition (MOCVD)

SrTiO 3 thin films with thicknesses ranging from 30 nm to 60 nm were grown on 6-inch-diameter, platinized Si wafers by liquid source metal-organic chemical vapor deposition (MOCVD). The crystalline quality and cation concentrations of the films are strongly dependent on the deposition temperature with optimum temperatures ranging from 500°C to 550°C. Semi-conformal deposition on submicron-sized storage node patterns is obtained but further improvements in conformality and reproducibility are required. The dielectric constant is about 210 irrespective of the film thickness and leakage current densities are sufficiently small for the dynamic random access memory (DRAM) applications. SiO 2 equivalent thickness (T ox ) of the 30-nm-thick STO film is 0.51 nm. The finding that the leakage current density and dielectric constant are independent of the film thickness can be explained by a fully depleted model of the STO film.