Wan-Don Kim

Conformal CVD-ruthenium process for MIM capacitor in giga-bit DRAMs

To realize the gigabit-scale DRAM capacitor, it is necessary to develop new electrode materials instead of poly-Si and TiN. Among them, Ruthenium has been the most promising electrode material in advance of Pt or Ir because it can be easily etched by oxygen plasma and shows good electrical properties as a capacitor electrode. But, a CVD-Ru film with good conformality and smooth morphology actually applicable to gigabit-scale DRAM generations has not been known up to now. In this work, we present the development of novel CVD process for application in real device with 3-dimensional structure and the electrical properties of capacitor using CVD-Ru electrode.

Electrical Properties of Crystalline Ta2O5 with Ru Electrode

As one candidate capacitor for dynamic random access memories (DRAMs) of 4 Gbit and beyond, we investigated the electrical properties of Ru/Ta2O5/Ru. In this paper, the dielectric constant of Ta2O5 was measured as a function of annealing temperature and, also, its dependence on film thickness was studied. The effect of postannealing, which was performed after forming a capacitor, on the leakage current of Ru/crystalline-Ta2O5/Ru capacitor was evaluated. Additionally, the leakage current was investigated as a function of Ta2O5 film thickness. Through these experiments, a reliable 7 A Toxeq. of Ta2O5 with a Ru electrode was obtained, which indicates that the Ru/crystalline-Ta2O5/Ru capacitor is a promising candidate for DRAMs of 4 Gbit and beyond.

Rugged Metal Electrode (RME) for High Density Memory Devices

Rugged metal electrode (RME) was suggested and evaluated as a bottom electrode of high-density memory capacitors. Rugged ruthenium films (RME-Ru) were successfully fabricated through volume shrinking of ruthenium oxide films under reduction ambient (RuOx+H2=Ru+H2O). The effective surface area of RME-Ru films was significantly enlarged due to the formation of wrinkle on its surface, which resulted in low SiO2 equivalent thickness (Tox) as low as ~ 6 A with Ru/TaOx(110 A)/RME-Ru capacitor. It is believed that RME technique will be very useful to realize and extend MIM (Metal-Insulator-Metal) capacitor era in the mass production of high density memory devices.

Evaluation of Novel Sr Precursors for Atomic Layer Deposition of SrO Thin Film

Atomic layer deposition (ALD) process to deposit SrO film using novel Sr precursor – Sr (Methoxy-TetramethylHeptadiene)2 was estimated. Fig.1 showed the chemical structure of the synthesized Sr(MTHD)2. Fig. 2 showed thermal gravimetric analysis results of Sr(MTHD)2 and commercially used Sr (Tetra-Methyl Hetadiene)2. 50 % precursor evaporation temperature (T50) of Sr (MTHD)2 was 330 C, which was 30 C lower than that of Sr(TMHD)2. Liquid delivery system with flash evaporator was used to transport the precursors to substrate. The precursors were dissolved in Tetra Hydro Furan (THF) to prevent clogging during the delivery process. Ozone was used as a reactant to deposit SrO. It was found that thickness uniformity range of SrO film on Si wafer was less than 2 %. The deposition rate of SrO film using new Sr precursor was 0.4 A/cycle, which was almost same regardless of substrate temperatures up to 400 C. High vapor pressure and good thermal stability of new Sr precursor make it promising candidates for ALD precursors to deposit SrTiO3, aSrTiO3. Fig.1. Chemical structure of Sr(MTHD)2

Ru/TiO2/ZrO2/TiN (RIT-TiO2/ZrO2) Capacitor Structure for the 50nm DRAM Device and beyond

Advanced Process Development Team, *Process Development Team, Semiconductor R&D Division, Samsung Electronics Co., Ltd. San#24 Nongseo-Dong, Giheung-Gu, Yongin-City, Gyeonggi-Do, Korea 449-711 E-mail: soon310.lim@samsung.com Introduction As the innovative scale-down of DRAM device continues, 50nm generation becomes close at hand. As shown in Fig. 1, to satisfy the cell capacitance of 25fF with 1.7μm storage-node height in 50nm design rule, the equivalent oxide thickness (Toxeq.) of a dielectric material should be as low as 0.8nm. TiN/HfO2/TiN (TIT) capacitor has been successfully developed for 70nm generation [1], but it seems to be difficult to meet the requirements for sub-60nm device. When Ta2O5 or TiO2 was implemented as the dielectric of the TIT capacitor to reduce Toxeq. below 1.2nm, it was difficult to suppress the leakage current because of low barrier height and poor interface between TiN and high-k dielectric (Figure 2). On the other hand, Ru/Insulator/Ru (RIR) capacitor using high-k dielectrics has some problems yet to be solved, such as the contact-plug oxidation and Ru electrode agglomeration during the back-end process. In the previous study [2], we have proposed Ru(top)/Insulator/TiN(bottom) capacitor as an alternative for the DRAM capacitor below 50nm generation. The leakage currents of Ta2O5 and TiO2 could be reduced by the application of Ru top electrode. And also a reliable storage-node was obtained with solid TiN bottom electrode. RIT-Ta2O5/HfO2 was successfully developed corresponding to Toxeq. 1.1nm with 1fA/cell leakage current after full integration. In this study, to reduce Toxeq. value lower than 0.8nm, we have introduced ZrO2 as dielectric layers. We have compared and discussed the electrical characteristics of RIT-TiO2/ZrO2 and RIT-TiO2/HfO2 capacitors. The electrical properties after back-end metal-line integration and time-dependent-dielectricbreakdown behavior were also investigated .

Development of CVD-Ru/Ta/sub 2/O/sub 5//CVD-Ru capacitor with concave structure for multigigabit-scale DRAM generation

RIR(Ru/Crystalline-Ta/sub 2/O/sub 5/Ru) capacitor with concave structure was studied for the application into multigigabit-scale DRAM device. In this work, several novel technologies were successfully developed to solve current issues in the fabrication of RIR concave capacitor; such as 1) two-step deposition of Ta/sub 2/O/sub 5/ films 2) formation of Ta/sub 2/O/sub 5/ spacer 3) new separation process of Ru storage node using maskless etch-back method 4) H/sub 2/ pre-annealing and 5) Ar plasma pre-treatment on Ru bottom electrode. The RIR concave capacitor (design rule/spl sim/0.12 /spl mu/m, node height/spl sim/0.85 /spl mu/m) fabricated with these novel technologies showed excellent electrical properties (25fF/cell, 1fA/cell at /spl plusmn/ 1V), which indicates that RIR structure is the one of the most promising candidate for the next generation DRAM capacitor.

Development of Ru/Ta/sub 2/O/sub 5//Ru capacitor technology for giga-scale DRAMs

In this paper, the Ru/crystalline-Ta/sub 2/O/sub 5//Ru capacitor was investigated. We studied the electrical properties and introduced an Al/sub 2/O/sub 3/ capping layer to prohibit the degradation of the leakage current resulted from H/sub 2/ annealing. Also, the Ru cylinder-type structure was suggested as a 3-dimensional storage node shape and was confirmed in its extendibility to 0.1 /spl mu/m-scaled design rule.