Hideki Takase

Partitioning and allocation of scratch-pad memory for priority-based preemptive multi-task systems

Scratch-pad memory has been employed as a partial or entire replacement for cache memory due to its better energy efficiency. In this paper, we propose scratch-pad memory management techniques for priority-based preemptive multi-task systems. Our techniques are applicable to a real-time environment. The three methods which we propose, i.e., spatial, temporal, and hybrid methods, bring about effective usage of the scratch-pad memory space, and achieve energy reduction in the instruction memory subsystems. We formulate each method as an integer programming problem that simultaneously determines (1) partitioning of scratch-pad memory space for the tasks, and (2) allocation of program code to scratch-pad memory space for each task. It is remarkable that periods and priorities of tasks are considered in the formulas. Additionally, we implement an RTOS-hardware cooperative support mechanism for a runtime code allocation to the scratch-pad memory space. We have made the experiments with the fully functional real-time operating system. The experimental results with four task sets have demonstrated the effectiveness of our techniques. Up to 73 % energy reduction compared to a standard method was achieved.

Minimizing inter-task interferences in scratch-pad memory usage for reducing the energy consumption of multi-task systems

This paper presents a new technique for reducing the energy consumption of a multi-task system by sharing its scratchpad memory (SPM) space among the tasks. With this technique, tasks can interfere by using common areas of the SPM. However, this requires to update these areas during context switches, which involves considerable overheads. Hence, an integer linear programming formulation is used at compile time for finding the best assignment of memory objects to the SPM and their respective locations inside it. Experiments show that the technique achieves up to 85% energy reduction with 8Kb of SPM and surpasses other sharing approaches.

An integrated optimization framework for reducing the energy consumption of embedded real-time applications

This paper presents a framework for the purpose of energy optimization of embedded real-time systems. We implemented the presented framework as an optimization toolchain and an energy-aware real-time operating system. Our framework is synthetic, that is, multiple techniques optimize the target application together. The main idea of our approach is to utilize a trade-off between energy and performance of the processor configuration. The optimal processor configuration is selected at each appropriate point in the task. Additionally, an optimization technique about the memory allocation is employed in our framework. Our framework is also gradual, that is, the target application is optimized in a step-by-step manner. The characteristic and the behavior of target applications are analyzed and optimized for both intra-task and inter-task levels by our toolchain at the static time. Based on the results of static time optimization, the runtime energy optimization is performed by a real-time operating system according to the behavior of the application. A case study shows that energy minimization is achieved on average while keeping the real-time performance.

Checkpoint Extraction Using Execution Traces for Intra-task DVFS in Embedded Systems

It is important to estimate accurately the remaining worst case execution cycles in a program to improve the effect that intra-task dynamic voltage and frequency scaling (DVFS) has on energy reduction. Since checkpoints for DVFS involve execution time and energy overhead, it is necessary to calculate where those checkpoints should be inserted in the program and the processor frequency at each execution path. To address this issue, we propose the use of execution trace mining to extract the initial checkpoint candidates. Moreover, we introduce a greedy algorithm to further select the checkpoints with highest energy reduction efficiency. Experimental results using Media Bench tests validate the effectiveness of our method.

Partitioning and Allocation of Scratch-Pad Memory in Priority-Based Multi-Task Systems

This paper proposes three approaches for allocation of scratch-pad memory in non-preemptive fixed-priority multi-task systems. These approaches can reduce energy consumption of instruction memory. Each approach is formulated as an integer programming problem which simultaneously determines (1) partitioning of scratch-pad memory spaces for the tasks, and (2) allocation of functions to the scratch-pad memory space for each task. The experimental results show the effectiveness of the proposed approaches.

Allocation of scratch-pad memory in priority-based multi-task systems

This paper proposes three approaches for allocation of scratch-pad memory in non-preemptive fixed-priority multi-task systems. These approaches can reduce energy consumption of instruction memory. Each approach is formulated as an integer programming problem which simultaneously determines (1) partitioning of scratch-pad memory spaces for the tasks, and (2) allocation of functions to the scratch-pad memory space for each task. The experimental results show the effectiveness of the proposed approaches.

Energy Efficiency of Scratch-Pad Memory at 65 nm and Below: An Empirical Study

A number of approaches have been proposed so far for reducing the energy consumption of embedded systems by using scratch-pad memory. However, most of previous work focused on dynamic energy reduction, and did not take enough consideration of the leakage energy in their evaluations. As the technology scales down to the deep submicron domain, the leakage energy in memory devices could contribute to a significant portion of the total energy consumption. Therefore, evaluation of energy consumption including the leakage energy is necessary. In this paper, we investigate the effectiveness of scratch-pad memory on energy reduction considering both the dynamic and leakage energy. The experiments are performed for 65 nm, 45 nm, and 32 nm technologies. The results demonstrate the effectiveness of scratch-pad memory in deep submicron technology. It is also observed that the leakage energy becomes less significant along with the technology scaling.

Energy efficiency of scratch-pad memory in deep submicron domains: an empirical study

As the technology scales down to the deep submicron domain, the leakage energy in memory devices could contribute to a significant portion of the total energy consumption. Therefore, evaluation of energy consumption including the leakage energy is necessary. In this paper, we investigate the effectiveness of scratch-pad memory on energy reduction considering both the dynamic and leakage energy. The experiments are performed for 65nm, 45nm, and 32nm technologies. The results demonstrate the effectiveness of scratch-pad memory in deep submicron technology. It is also observed that the leakage energy becomes less significant along with the technology scaling.

Efficient Algorithms for Extracting Pareto-optimal Hardware Configurations in DEPS Framework

A dynamic energy performance scaling (DEPS) framework has been proposed as a generalization of dynamic voltage frequency scaling (DVFS). The DEPS framework selects an energy-optimal hardware configuration at runtime. To reduce runtime overhead, Pareto-optimal combinations of hardware configurations should be provided via DEPS profiling during the design phase. The challenge of DEPS profiling lies in extracting the Pareto-optimal combinations efficiently from the exponential search space. We propose two exact algorithms to reduce the number of calculations in DEPS profiling. These algorithms can be used with common search algorithms. We also propose a heuristic algorithm for searching Pareto-optimal configurations efficiently. Extensive experiments are performed, and they demonstrate that the proposed algorithms can complete DEPS profiling within a reasonable amount of time and generate optimal DEPS profiles. It is believed that the proposed algorithms will enable easy application of the DEPS framework in practice.

History of summer school on embedded system technologies organized by students and young engineers

This paper reports an embedded educational activity named Summer School on Embedded System Technologies (SSEST) in Japan. We, the committee members made up of students and young engineers gathering from all over the country, set down beginners as main targets since they have few chance to experience a series of processes of an embedded system development. This activity aims to provide an opportunity to learn elementary knowledge and skills of embedded system technologies through a practice of whole development process. Communication skills of participants can be enhanced by an interchange among them of different universities and companies through a group work. In this paper, we introduce a learning curriculum and contents of SSEST. Our curriculum consists of prior individual training and boot camp. Participants develop a line trace car through the embedded system development process. Then, we discuss the educational effects on this activity and achievements of the purpose. According to answers of the questionnaire, the 94% of participants satisfied or almost satisfied for SSEST.